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| author | Camil Staps | 2016-11-15 23:45:33 +0100 |
|---|---|---|
| committer | Camil Staps | 2016-11-15 23:45:33 +0100 |
| commit | e582e8e9d7e1b8e7025cfc4b58ba687491d3b3f2 (patch) | |
| tree | 7bd695b8d8641f8ff8524a00b583d65228ee0b20 /thesis/two-bits.tex | |
| parent | Thesis: introduction, two LSBs (diff) | |
Lot of formatting; rewriting storing-pc; references; natbib -> biblatex; autoref -> cref; minted; etc.
Diffstat (limited to 'thesis/two-bits.tex')
| -rw-r--r-- | thesis/two-bits.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/thesis/two-bits.tex b/thesis/two-bits.tex index 4b08d89..fcd4046 100644 --- a/thesis/two-bits.tex +++ b/thesis/two-bits.tex @@ -13,7 +13,7 @@ Instructions are halfword-aligned, so bit 1 is part of the address. Additionally, bit 0 is used to facilitate ARM and Thumb interworking. When the PC is written to with a value where the LSB is cleared, the processor jumps and switches to ARM mode. -When the LSB is set, it switches to Thumb mode~\citep[A2.3.2]{armv7ar}. +When the LSB is set, it switches to Thumb mode~\parencite[A2.3.2]{armv7ar}. \subsection{Usage in Clean} \label{sec:two-bits:clean} |