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| -rw-r--r-- | thesis/abbr.tex | 4 | ||||
| -rw-r--r-- | thesis/clean.sty | 1 | ||||
| -rw-r--r-- | thesis/fix-storing-pc.tex | 87 | ||||
| -rw-r--r-- | thesis/intro.tex | 129 | ||||
| -rw-r--r-- | thesis/results.tex | 6 | ||||
| m--------- | thesis/rutitlepage | 0 | ||||
| -rw-r--r-- | thesis/storing-pc.tex | 150 | ||||
| -rw-r--r-- | thesis/thesis.bib | 41 | ||||
| -rw-r--r-- | thesis/thesis.tex | 52 | ||||
| -rw-r--r-- | thesis/two-bits.tex | 2 | ||||
| -rw-r--r-- | thesis/ual.sty | 2 |
12 files changed, 329 insertions, 146 deletions
@@ -4,6 +4,7 @@ *.alg *.aux *.bbl +*.bcf *.blg *.dvi *.fdb_latexmk diff --git a/thesis/abbr.tex b/thesis/abbr.tex index 0c172ef..d66f06a 100644 --- a/thesis/abbr.tex +++ b/thesis/abbr.tex @@ -6,6 +6,8 @@ Head normal form, the state of a graph node that cannot be rewritten itself (though it children may). \item[ISA] Instruction set architecture. + \item[IT block] + If-then block, a Thumb construct for conditional execution. \item[LSB(s)] Least significant bit(s), the bit(s) with the lowest value in a word. \item[PC] @@ -15,6 +17,6 @@ Clean's run-time system ensures that the \clean{Start} node is reduced and printed. It also takes care of garbage collecting. \item[UAL] - Unified Assembly Language. + Unified Assembler Language. %todo \end{description} diff --git a/thesis/clean.sty b/thesis/clean.sty index 2451bbd..a9c0e03 100644 --- a/thesis/clean.sty +++ b/thesis/clean.sty @@ -1,5 +1,6 @@ \RequirePackage{minted} \newmintinline[clean]{clean}{style=bw} +\newmintinline[abc]{text}{style=bw} \RequirePackage{tikz} \pgfkeys{/tikz/node args/.store in=\clean@args} diff --git a/thesis/fix-storing-pc.tex b/thesis/fix-storing-pc.tex deleted file mode 100644 index 31381f0..0000000 --- a/thesis/fix-storing-pc.tex +++ /dev/null @@ -1,87 +0,0 @@ -\section{Storing the program counter} -\label{sec:fix-storing-pc} - -\begin{multicols}{2} - -The first issue I ran into is that of storing the program counter. -Storing the program counter on the stack is something done commonly in many languages during a function call. - -\subsection{ARM code example} -Usually, an offset to the actual program counter at the moment of the store instruction is stored, -to allow for a branch after that instruction, and have the callee return to the address after that branch. -The ARM architecture accommodates for this: an instruction that reads the program counter, actually reads - \enquote{the address of the current instruction plus 8}~\cite[A2.3]{armv7ar}. -The following ARM assembly example illustrates this (\texttt{armstartup.s:540-2},~\cite{armrts}): - -\begin{minted}{ual} - str pc,[sp,#-4]! - bl init_clean - tst r4,r4 -\end{minted} - -\begin{lrbox}{\ualbox} - \ual{[sp,#-4]!} -\end{lrbox} - -Dummy addresses have been indicated in comments. -When execution arrives at \ual{0x20}, the program counter is set to \ual{0x20}. -Per the above documentation, \ual{str} stores \ual{0x20+8} on the stack% - \footnote{\usebox{\ualbox} - indicates that the stack pointer should be decreased by four before storing the program counter on the stack. - It has nothing to do with the 8 offset that is added to the program counter itself.}. -The processor branches to \ual{init_clean}, - which loads the value from the stack back into the program counter to return to the caller. -The program counter is then \ual{0x28}. -For the next instruction cycle, the \ual{tst} command is executed. - -\subsection{Adapting for Thumb-2} -There are two reasons why the above cannot be used in Thumb-2 code. - -First, \ual{pc} is not allowed as the first operand to a \ual{str} instruction. -Hence, we need to first move \ual{pc} to an auxiliary register, and then push that on the stack. -We then get: - -\begin{minted}{ual} - add lr,pc,#9 - str lr,[sp,#-4]! - bl init_clean - tst r4,r4 -\end{minted} - -We store the value \ual{0x2d}. -This address points to the \ual{tst} instruction as before, with the LSB set to 1 to indicate Thumb mode. - -The second problem we meet is that the instruction to store the program counter may be halfword-aligned rather than word-aligned. -We saw above that a read of the program counter in ARM mode reads as PC+8. -In Thumb mode this is more complicated. -In this case, we - \enquote{[r]ead the word-aligned PC value, that is, - the address of the current instruction + 4, - with bits [1:0] forced to zero}~\cite[A5.1.2]{armv7m}. -This means that when the \ual{add} instruction above is at \ual{0x22}, - we will still store \ual{0x2d} on the stack, - since the word-aligned program counter is \ual{0x20} as before. -However, in this case \ual{bl} is located at \ual{0x2a}, and since this is a 32 bits instruction we point to the middle of that instruction. - -In hand-written code, we can solve this by adding labels for the addresses we want to store on the stack. -In generated code, we need to keep track of the current alignment and add either 9 or 11 to the read program counter. - -\subsection{Other solutions} -Another solution than the one we present here is the use of the link register. -Branch instructions as \ual{bl} store the address of the next instruction in the link register. -We could therefore imagine a setup where the callee gets the return address from that register rather than from the stack. -This is the approach taken by GCC. -The code of a typical C subroutine starts with \ual{push {r7,lr}} and ends with \ual{pop {r7,pc}}. - -When generating code for a functional language, this is not easily done due to tail recursion. -It is an easier solution to have the caller responsible for storing the return address, - which is why this approach is taken in Clean's ARM code generator\cite{armcg} - and why I continue along those lines. - -\subsection{Complexity analysis} -To be done. %TODO - -For every occurrence: +1 word code size; -for every function call: +1 instruction. - -\end{multicols} diff --git a/thesis/intro.tex b/thesis/intro.tex index 0b75b49..8640811 100644 --- a/thesis/intro.tex +++ b/thesis/intro.tex @@ -1,7 +1,72 @@ \section{Introduction} \label{sec:intro} -\begin{figure*}[b] +\begin{multicols}{2} + +\subsection{Introduction} +\label{sec:intro:intro} +The Thumb-2 instruction set combines the best features of the ARM and Thumb instruction sets (speed and small code size, respectively). +We discuss the differences between the ARM and Thumb-2 instruction sets, + and their influences on code generation. +Specifically, we look at code generation for the purely functional programming language Clean. +%todo results + +\subsection{ARM, Thumb and Thumb-2} +\label{sec:intro:arm-thumb-thumb2} +ARM is a RISC architecture with several enhancements to a basic RISC architecture allowing ARM processors to + \enquote{achieve a good balance of high performance, small program size, low power consumption, and small silicon area}~\parencite[A1.1]{armv7ar}. + +Several instruction sets were designed for the ARM architecture. +First of all, the 32-bit ARM ISA allows the programmer to easily make full use of all the architecture's features. +The Thumb instruction set provides a 16-bit alternative to the ARM ISA, giving in on performance to achieve improved code density. +Starting from ARMv6T2, an extension to the Thumb instruction set, known as Thumb-2, adds 32-bit instructions to Thumb to + \enquote{achieve performance similar to ARM code, with code density better than that of earlier Thumb code}~\parencite[A1.2]{armv7ar}. +This gives the ARM and Thumb instruction sets \enquote{almost identical functionality}~\parencite[A1.2]{armv7ar}, + whereas Thumb gives a smaller code size. + +Using the Unified Assembler Language (UAL), one can write assembly code for both the ARM and the Thumb instruction set and fix the target ISA only at assemble-time. + +The main differences between ARM and Thumb-2 are the following: + +\subsubsection{Conditional execution} +\label{sec:intro:conditionals} +In ARM, every instruction has a 4-bit conditional field that allows for conditional execution. +In the Thumb instruction set, all conditional instructions except branches have to be in an \enquote{IT block}. +A first \ual{it} instruction gives the base condition and a then-else pattern. +The following instructions are executed conditionally. +For example: + +\begin{minted}{ual} + itte gt @ tte: then, then, else + movgt r2,r3 @ mov if gt + movgt r0,r1 @ mov if gt + movle r0,#0 @ mov if le (= not gt) +\end{minted} + +This is UAL syntax. +When assembling for Thumb, an \ual{it} instruction with three \ual{mov} instructions (without conditional field) is generated. +For ARM, the \ual{it} instruction is ignored and three conditional \ual{mov} instructions are generated. + +%ARMv8-A deprecates some uses of the \ual{it} instruction for performance reasons~\parencite[J5.2]{armv8a}. + +\subsubsection{Register usage} +\label{sec:intro:registers} +ARM processors have sixteen registers. +ARM instructions have 4-bit register fields to address them. +Some 16-bit Thumb instructions have 3-bit register fields that can only address the lowest eight registers. +For these instructions there exist 32-bit variants that can address all sixteen registers. + +\subsubsection{Interworking} +\label{sec:intro:interworking} +The ARM and Thumb instruction sets are designed to \emph{interwork}: + different parts of a program can be assembled for different instruction sets + and it is possible to switch instruction set when the program counter is written to~\parencite[A4.1]{armv7ar}. + +The Thumb-2 code generator proposed in this thesis does not produce ARM code, + though the existence of the interworking facility has effects on the techniques that can be used in it. +This will be covered in \cref{sec:two-bits}. + +\begin{figure*} \centering \begin{subfigure}[b]{.2\linewidth} \centering @@ -51,43 +116,10 @@ \caption{Rewriting a Clean node\label{fig:intro:rewriting}} \end{figure*} -\begin{multicols}{2} - -\subsection{Introduction} -\label{sec:intro:intro} -The Thumb-2 instruction set combines the best features of the ARM and Thumb instruction sets (speed and small code size, respectively). -We discuss the differences between the ARM and Thumb-2 instruction sets, - and their influences on code generation. -Specifically, we look at code generation for the purely functional programming language Clean. -%todo results - -\subsection{ARM, Thumb and Thumb-2} -\label{sec:intro:arm-thumb-thumb2} -ARM is a RISC architecture with several enhancements to a basic RISC architecture allowing ARM processors to - `achieve a good balance of high performance, small program size, low power consumption, and small silicon area'~\citep[A1.1]{armv7ar}. - -Several instruction sets were designed for the ARM architecture. -First of all, the 32-bit ARM ISA allows the programmer to easily make full use of all the architecture's features. -The Thumb instruction set provides a 16-bit alternative to the ARM ISA, giving in on performance to achieve improved code density. -Starting from ARMv6T2, an extension to the Thumb instruction set, known as Thumb-2, adds 32-bit instructions to Thumb to - `achieve performance similar to ARM code, with code density better than that of earlier Thumb code'~\citep[A1.2]{armv7ar}. -This gives the ARM and Thumb instruction sets `almost identical functionality'~\citep[A1.2]{armv7ar}, - whereas Thumb gives a smaller code size. - -Using the Unified Assembly Language (UAL), one can write assembly code for both the ARM and the Thumb instruction set and fix the target ISA only at assemble-time. - -\label{sec:intro:interworking} -The ARM and Thumb instruction sets are designed to \emph{interwork}: - different parts of a program can be assembled for different instruction sets - and it is possible to switch instruction set when the program counter is written~\citep[A4.1]{armv7ar}. -The Thumb-2 code generator proposed in this thesis does not produce ARM code, - though the existence of the interworking facility has effects on the techniques that can be used in it. -This will be covered in \autoref{sec:two-bits}. - \subsection{Clean} \label{sec:intro:clean} -Clean is `a general purpose, state-of-the-art, pure and lazy functional programming language designed for making real-world applications'~\cite{clean}. -It evolved from LEAN, an intermediate language based on graph rewriting~\citep{lean}. +Clean is \enquote{a general purpose, state-of-the-art, pure and lazy functional programming language designed for making real-world applications}~\parencite{clean}. +It evolved from LEAN, an intermediate language based on graph rewriting~\parencite{lean}. A Clean program consists of a list of rewrite rules, for example: \begin{minted}{clean} @@ -97,9 +129,9 @@ A Clean program consists of a list of rewrite rules, for example: \end{minted} Executing a Clean program means rewriting the \clean{Start} rule until no rewriting is possible any more. -The first rewriting steps of the above program are shown in \autoref{fig:intro:rewriting}. +The first rewriting steps of the above program are shown in \cref{fig:intro:rewriting}. -A Clean program is compiled to ABC-code, a platform-independent bytecode for an abstract graph rewriting machine~\citep{execspecs}. +A Clean program is compiled to ABC-code, a platform-independent bytecode for an abstract graph rewriting machine~\parencite{execspecs}. A code generator is used to generate machine code equivalent to the ABC-code for concrete machines. This, again, is done in several steps, so that only a relatively small part of the compilation process is target-dependent. For adapting the ARM code generator to work for Thumb-2 one needs to have only very basic knowledge of the ABC-machine. @@ -114,30 +146,39 @@ This system is written in C and assembly, so making Clean available on Thumb-2 i \label{sec:intro:clean-thumb} In this thesis, we propose a Thumb backend for Clean. The ARM code generator and RTS were taken as a starting point. -Thanks to the Unified Assembly Language, only little time was needed to make these systems assemble for the Thumb instruction set. +Thanks to the Unified Assembler Language, only little time was needed to make these systems assemble for the Thumb instruction set. The proposed backend does not use ARM and Thumb interworking. The reason for this is threefold. -First, there are several processors, like the ARMv7-M series~\citep[A4.1]{armv7m}, that do support Thumb instructions but cannot run ARM code. +First, there are several processors, like the ARMv7-M series~\parencite[A4.1]{armv7m}, that do support Thumb instructions but cannot run ARM code. By only using Thumb, we target the widest possible range of devices. Second, we doubt that using interworking can be done efficiently. In the run-time system, only minimal time overhead is introduced by using Thumb instructions. For generated code it would be complicated to detect if the ARM or Thumb instruction set would give better results, and this would give significantly better results only in specific cases. -Third, the problem discussed in \autoref{sec:two-bits} could be solved efficiently only without interworking. +Third, the problem discussed in \cref{sec:two-bits} could be solved efficiently only without interworking. Using interworking would introduce overhead at every branch instruction, since the solution to this problem would have to be adapted. \subsection{Terminology} \label{sec:intro:terminology} -In this thesis, I will usually write `Thumb' where the Thumb-2 extension is meant. +In this thesis, I will usually write \enquote{Thumb} where the Thumb-2 extension is meant. Only when the distinction with pre-ARMv6T2 Thumb is important will I distinguish between (early) Thumb and Thumb-2. -As for `ARM', it should be clear from the context whether the architecture or the instruction set is meant. +As for \enquote{ARM}, it should be clear from the context whether the architecture or the instruction set is meant. For brevity, a number of common abbreviations is used. -An overview can be found in \autoref{sec:abbreviations}. +An overview can be found in \cref{sec:abbreviations}. \subsection{Organisation} \label{sec:intro:organisation} +In much of the rest of this thesis we discuss differences between ARM and Thumb, + their influences on code generation, + and the way they were dealt with in the Thumb backend for Clean proposed in this thesis. +In \cref{sec:storing-pc}, we consider an issue arising from halfword-aligned instructions and the way a read of PC is interpreted under Thumb. +\Cref{sec:two-bits} discusses problems related to the fact that Thumb instruction addresses use bit 1 and should have bit 0 set for interworking, + while under ARM a branch will automatically clear both these bits. + +The Thumb backend for Clean has been benchmarked. +The results are collected and discussed in \cref{sec:results}. \end{multicols} diff --git a/thesis/results.tex b/thesis/results.tex new file mode 100644 index 0000000..561de6c --- /dev/null +++ b/thesis/results.tex @@ -0,0 +1,6 @@ +\section{Results} +\label{sec:results} + +\begin{multicols}{2} + +\end{multicols} diff --git a/thesis/rutitlepage b/thesis/rutitlepage -Subproject 516fa9e441801392e08a7328cb6196a8849724c +Subproject b6aa2bf105d774573dac37a810273fb225aa62a diff --git a/thesis/storing-pc.tex b/thesis/storing-pc.tex new file mode 100644 index 0000000..98b03ae --- /dev/null +++ b/thesis/storing-pc.tex @@ -0,0 +1,150 @@ +\section{Storing the program counter} +\label{sec:storing-pc} + +\begin{multicols}{2} + +\subsection{Introduction} +\label{sec:storing-pc:intro} +Storing the program counter on the stack is something done commonly in many languages during a function call. +Usually, an offset to the actual program counter at the moment of the store instruction is stored, + to allow for a branch after that instruction, and have the callee return to the address after that branch. +The ARM architecture accommodates for this: an ARM instruction that reads the program counter, actually reads + \enquote{the address of the current instruction plus 8}~\parencite[A2.3]{armv7ar}. +The following ARM assembly example illustrates this (\texttt{armstartup.s:540-2},~\cite{armrts}): + +\begin{minted}{ual} + str pc,[sp,#-4]! @ 0x20 + bl init_clean @ 0x24 + tst r4,r4 @ 0x28 +\end{minted} + +Dummy addresses have been indicated in comments. +When execution arrives at \ual{0x20}, the program counter is set to \ual{0x20}. +Per the above documentation, \ual{str} stores \ual{0x20+8} on the stack + (to be precise: to the address indicated by the stack pointer with pre-indexed offset \ual{-4}). +The processor branches to \ual{init_clean}, + which loads the value from the stack back into the program counter to return to the caller. +The program counter is then \ual{0x28}. +For the next instruction cycle, the \ual{tst} command is executed. + +There are two reasons why the above cannot be used in Thumb-2 code. +First, \ual{pc} is not allowed as the first operand of a \ual{str} instruction. + +The second problem we meet is that the instruction to store the program counter may be halfword-aligned rather than word-aligned. +We saw above that a read of the program counter in ARM mode reads as PC+8. +In Thumb mode this is more complicated. +In this case, we + \enquote{[r]ead the word-aligned PC value, that is, + the address of the current instruction + 4, + with bits [1:0] forced to zero}~\parencite[A5.1.2]{armv7m}. +This means that when the \ual{add} instruction above is at \ual{0x22}, + we will still store \ual{0x2d} on the stack, + since the word-aligned program counter is \ual{0x20} as before. +However, in this case \ual{bl} is located at \ual{0x2a}, and since this is a 32 bits instruction we point to the middle of that instruction. + +\subsection{Usage in Clean} +\label{sec:storing-pc:clean} +Storing the PC is required for jumping to subroutines. +We see a clear example of this when a Clean function definition uses pattern matching. +Consider the following example: + +\begin{minted}{clean} + isEmpty :: [a] -> Bool + isEmpty [] = True + isEmpty _ = False +\end{minted} + +The generated ABC-code looks as below% + \footnote{The current Clean compiler misses the \abc{jsr_eval 0} line: + the strictness analyser recognises that \clean{isEmpty} is strict in its first argument, + so evaluating the argument to head normal form is not needed any more. + In cases where the strictness analyser cannot derive strictness, + code similar to this example is generated. + The code given here can be reproduced with \bash{clm -nsa}.}. +Since \clean{isEmpty} pattern matches on its first argument, it needs to be evaluated to head normal form. +This is done with \abc{jsr_eval 0}. +Only after that can we check if its constructor is \abc{_Nil} (the empty list), which is done with \abc{eq_desc _Nil 0 0}. + +\begin{minted}[tabsize=4]{text} + sisEmpty.1 + jsr_eval 0 || Evaluate argument + eq_desc _Nil 0 0 || If it equals [] + jmp_true case.1 || .. jump to case.1 + jmp case.2 || [else] to case.2 + case.1 + pop_a 1 || Pop argument + pushB TRUE || Return True + rtn + case.2 + pop_a 1 || Pop argument + pushB FALSE || Return False + rtn +\end{minted} + +Evaluating the argument is done by jumping to the subroutine indicated by the node entry of that argument. +Hence, we store the PC, jump to that address, and continue with \abc{eq_desc _Nil 0 0} when the node has been evaluated to head normal form. +The ARM code for pattern matching is: + +\begin{minted}{ual} + sisEmpty_P1: + ldr r12,[r6] @ Load node entry point + tst r12,#2 @ If in HNF already + bne e_0 @ Skip evaluation + str pc,[sp,#-4]! @ Store PC + blx r12 @ Evaluate argument + e_0: + ldr r12,[r6] @ If it does not equal [] + ldr r14,=__Nil+2 + cmp r12,r14 + bne case_P2 +\end{minted} + +We can see here + (a) that evaluating a node requires a \abc{jsr_eval} ABC instruction, and + (b) that \abc{jsr} ABC instructions require storing the PC in ARM assembly. + +Of course, evaluating nodes is something that happens throughout the source code and has to be done all the time during the execution of a Clean program. +We therefore need a fast, small Thumb alternative for the ARM code. + +\subsection{Solution} +\label{sec:storing-pc:solution} +To solve the first problem, we need to first move \ual{pc} to an auxiliary register, and then push that on the stack. +We then get, for the example from \texttt{armstartup.s:540-2}: + +\begin{minted}{ual} + add lr,pc,#9 @ 0x20 + str lr,[sp,#-4]! @ 0x24 + bl init_clean @ 0x28 + tst r4,r4 @ 0x2c +\end{minted} + +We store the value \ual{0x2d}. +This address points to the \ual{tst} instruction as before, with the LSB set to 1 to indicate Thumb mode. + +In assembly code, we can solve this by adding labels for the addresses we want to store on the stack. +In object code, we need to keep track of the current alignment and add either 9 or 11 to the read program counter. + +The offset, 9, is calculated as the number of bytes to the instruction after the branch plus one for Thumb mode. +For \ual{b} and \ual{bl} instructions, this means an offset of 9, since these instructions are 32-bit. +The \ual{bx} and \ual{blx} instructions are 16-bit, and require an offset of 7. + +\subsection{Other solutions} +\label{sec:storing-pc:other-solutions} +Another solution than the one we present makes use of the link register. +Some branch instructions, like \ual{bl}, store the address of the next instruction in the link register. +We could therefore imagine a setup where the callee gets the return address from that register rather than from the stack. +This is the approach taken by GCC. +The code of a typical C subroutine starts with \ual{push {...,lr}} and ends with \ual{pop {...,pc}}. + +When generating code for a functional language, it is not straightforward to do this, due to tail recursion. +It is an easier solution to have the caller responsible for storing the return address, + which is why this approach is taken in Clean's ARM code generator~\parencite{armcg} + and why we continue along these lines for the Thumb backend. + +\subsection{Comparison} +To be done. %TODO + +For every occurrence: +1 word code size; +for every function call: +1 instruction. + +\end{multicols} diff --git a/thesis/thesis.bib b/thesis/thesis.bib index 24b604f..23b7875 100644 --- a/thesis/thesis.bib +++ b/thesis/thesis.bib @@ -1,20 +1,31 @@ @manual{armv7ar, + label="ARMv7-AR", title="ARM Architecture Reference Manual. ARMv7-A and ARMv7-R edition", organization="ARM Limited", year=1996 } @manual{armv7m, + label="ARMv7-M", title="ARMv7-M Architecture Reference Manual", organization="ARM Limited", year=2006 } -@misc{clean, - title="Clean", +@manual{armv8a, + label="ARMv8-A", + title="ARM Architecture Reference Manual. ARMv8, for ARMv8-A architecture profile (Beta)", + organization="ARM Limited", + year=2013 +} + +@Online{clean, + label="Clean", + key="Clean", organization="Radboud University Nijmegen", - howpublished="\url{http://clean.cs.ru.nl/}", - year=2004 + url="http://clean.cs.ru.nl/", + year=2004, + urldate="2016-11-15" } @article{lean, @@ -37,3 +48,25 @@ school="Radboud University Nijmegen", year=1990 } + +@Online{armcg, + key="ARM CG", + label="ARM CG", + title="Clean's ARM code generator", + subtitle="Revision 295", + organization="Radboud University Nijmegen", + url="https://svn.cs.ru.nl/repos/clean-code-generator", + year=2016, + urldate="2016-11-15" +} + +@Online{armrts, + key="ARM RTS", + label="ARM RTS", + title="Clean's ARM run-time system", + subtitle="Revision 387", + organization="Radboud University Nijmegen", + url="https://svn.cs.ru.nl/repos/clean-run-time-system", + year=2016, + urldate="2016-11-15" +} diff --git a/thesis/thesis.tex b/thesis/thesis.tex index 14ef5bd..1d2a54f 100644 --- a/thesis/thesis.tex +++ b/thesis/thesis.tex @@ -1,6 +1,6 @@ \documentclass[a4paper,twoside]{amsart} -\usepackage{geometry} +\usepackage[hmarginratio={3:2}]{geometry} \usepackage{multicol} \usepackage[T1]{fontenc} @@ -16,13 +16,45 @@ \definecolor{urlcolor}{rgb}{0,0,0.65} \usepackage[colorlinks=true,linkcolor=linkcolor,urlcolor=urlcolor,citecolor=citecolor]{hyperref} -\usepackage{natbib} +\usepackage{cleveref} +\crefname{figure}{figure}{figures} + +\usepackage[style=authoryear,backend=biber]{biblatex} +\bibliography{thesis} +\renewcommand\nameyeardelim{, } +\DefineBibliographyStrings{english}{% + urlseen={Retrieved} +} \usepackage{rutitlepage} \usepackage{latexgit} +\usepackage{minted} +\usepackage{mdframed} +% Need to patch mdframed, see http://tex.stackexchange.com/a/292090/23992 +\usepackage{xpatch} +\makeatletter +\xpatchcmd{\endmdframed} + {\aftergroup\endmdf@trivlist\color@endgroup} + {\endmdf@trivlist\color@endgroup\@doendpe} + {}{} +\makeatother +\definecolor{mintedbg}{rgb}{0.95,0.95,0.95} +\surroundwithmdframed[% + backgroundcolor=mintedbg, + linewidth=0pt, + skipabove=.5em,skipbelow=.5em]{minted} +\setminted{% + autogobble, + tabsize=4, + fontsize=\scriptsize, + style=lovelace + %bgcolor=mintedbg +} +\setmintedinline{fontsize=\footnotesize,bgcolor={}} \usepackage{ual} \usepackage{clean} +\newmintinline[bash]{bash}{style=bw} \usepackage{subcaption} \usepackage{tikz} @@ -36,7 +68,7 @@ {\centering\it This page intentionally left blank.\par} \vspace{\fill}} \makeatletter -\renewcommand*{\cleardoublepage}{\clearpage\if@twoside \ifodd\c@page +\renewcommand*{\cleardoublepage}{\clearpage\if@twoside \ifodd\c@page\else \blankpage\thispagestyle{empty}\newpage \if@twocolumn\hbox{}\newpage\fi\fi\fi} \makeatother @@ -57,7 +89,10 @@ authorstext={Author:}, authors={Camil Staps}, righttextheader={Supervisors:}, - righttext={prof.~dr.~dr.h.c.~ir.~M.J.~Plasmeijer and drs.~J.H.G.~van~Groningen}] + righttext={prof.~dr.~dr.h.c.~ir.~M.J.~Plasmeijer and drs.~J.H.G.~van~Groningen}, + pagenr=1] + +\setcounter{page}{2} \cleardoublepage @@ -67,9 +102,9 @@ \cleardoublepage \input{intro} +\input{storing-pc} \input{two-bits} -%\input{approach} -\input{fix-storing-pc} +\input{results} \cleardoublepage \appendix @@ -77,7 +112,8 @@ \cleardoublepage -\bibliographystyle{plainnat} -\bibliography{thesis} +\let\oldurl\url +\renewcommand{\url}[1]{{\small\oldurl{#1}}} +\printbibliography \end{document} diff --git a/thesis/two-bits.tex b/thesis/two-bits.tex index 4b08d89..fcd4046 100644 --- a/thesis/two-bits.tex +++ b/thesis/two-bits.tex @@ -13,7 +13,7 @@ Instructions are halfword-aligned, so bit 1 is part of the address. Additionally, bit 0 is used to facilitate ARM and Thumb interworking. When the PC is written to with a value where the LSB is cleared, the processor jumps and switches to ARM mode. -When the LSB is set, it switches to Thumb mode~\citep[A2.3.2]{armv7ar}. +When the LSB is set, it switches to Thumb mode~\parencite[A2.3.2]{armv7ar}. \subsection{Usage in Clean} \label{sec:two-bits:clean} diff --git a/thesis/ual.sty b/thesis/ual.sty index 3318035..096fafe 100644 --- a/thesis/ual.sty +++ b/thesis/ual.sty @@ -1,6 +1,6 @@ \RequirePackage{minted} -\setminted{fontsize=\footnotesize,style=lovelace} +\setminted{tabsize=6} \newmintinline[ual]{ual}{style=bw} |