diff options
| author | Camil Staps | 2023-01-27 21:14:39 +0100 |
|---|---|---|
| committer | Camil Staps | 2023-01-27 21:15:57 +0100 |
| commit | bda2ff9eea470e7eb6dc573849dfc6abe8365069 (patch) | |
| tree | 1fa299d5be537c6dc33a4d9289d9358723cd5490 /snug-clean/src/MIPS/MIPS32.dcl | |
| parent | Add Clean parser for snug (diff) | |
Add compilation of constructors and basic values
Diffstat (limited to 'snug-clean/src/MIPS/MIPS32.dcl')
| -rw-r--r-- | snug-clean/src/MIPS/MIPS32.dcl | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/snug-clean/src/MIPS/MIPS32.dcl b/snug-clean/src/MIPS/MIPS32.dcl new file mode 100644 index 0000000..4789507 --- /dev/null +++ b/snug-clean/src/MIPS/MIPS32.dcl @@ -0,0 +1,96 @@ +definition module MIPS.MIPS32 + +from StdOverloaded import class toString + +:: Line + = StartSection !String + | Align !Int + | Label !Label + | Instr !Instruction + | RawWord !Int + | RawAscii !String + +instance toString Line + +:: Instruction + = LoadByte !Signedness !TargetRegister !Offset !Base + | LoadHalfword !Signedness !TargetRegister !Offset !Base + | LoadWord !TargetRegister !Offset !Base + | StoreByte !TargetRegister !Offset !Base + | StoreHalfword !TargetRegister !Offset !Base + | StoreWord !TargetRegister !Offset !Base + + | AddImmediate !Signedness !DestinationRegister !SourceRegister !Immediate + | AndImmediate !DestinationRegister !SourceRegister !Immediate + | LoadUpperImmediate !DestinationRegister !Immediate + | OrImmediate !DestinationRegister !SourceRegister !Immediate + | XorImmediate !DestinationRegister !SourceRegister !Immediate + + | AddWord !Signedness !DestinationRegister !SourceRegister !TargetRegister + | AndWord !DestinationRegister !SourceRegister !TargetRegister + | NorWord !DestinationRegister !SourceRegister !TargetRegister + | OrWord !DestinationRegister !SourceRegister !TargetRegister + | SubWord !Signedness !DestinationRegister !SourceRegister !TargetRegister + | XorWord !DestinationRegister !SourceRegister !TargetRegister + + | Jump !Link !JumpTarget + | BranchOn1 !BranchCondition1 !SourceRegister !Offset + | BranchOn2 !BranchCondition2 !SourceRegister !TargetRegister !Offset + + | Break !Int + | Syscall !Int /* applications should also set v0 to the syscall argument */ + + | LoadAddress !DestinationRegister !Immediate + | Nop + +Move rd rs :== OrImmediate rd rs (Immediate 0) + +instance toString Instruction + +:: Signedness + = Signed + | Unsigned + +:: Base :== Register +:: Offset :== Int /* 16-bit signed */ + +:: DestinationRegister :== Register +:: SourceRegister :== Register +:: TargetRegister :== Register + +:: Register + = R0 /* always zero */ + | AT /* reserved for assembler; do not use */ + | V0 | V1 /* expression evaluations, integer results, static link for nested procedures */ + | A !Int /* 0-3, integer arguments, values not preserved */ + | T !Int /* 0-9, temporary, values not preserved */ + | S !Int /* 0-7, saved, values preserved */ + | K0 | K1 /* reserved for the kernel */ + | GP /* global (heap) pointer */ + | SP /* stack pointer */ + | FP /* frame pointer if needed; otherwise saved register */ + | RA /* return address; temporary */ + +:: Immediate + = Immediate !Int /* 16-bit */ + | Address !Offset !Label + +:: Link + = Link + | NoLink + +:: JumpTarget + = Direct !Immediate + | Register !Register + +:: Label :== String + +:: BranchCondition1 + = BCGeZero !Link + | BCGtZero + | BCLeZero + | BCLtZero !Link + +:: BranchCondition2 + = BCEq + | BCNe |