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authorCamil Staps2017-07-19 12:57:01 +0000
committerCamil Staps2017-07-19 12:57:01 +0000
commit407a0c8e7e14b96c2a0487cefe09cdc021f002b0 (patch)
tree6f2f8eec4691c6c292f0cc77734729ac0b27fcf7 /Sil/Syntax.dcl
parentNomenclature: Application type is now Expression (diff)
Add while and !, fix error in consecutive declarations
Diffstat (limited to 'Sil/Syntax.dcl')
-rw-r--r--Sil/Syntax.dcl1
1 files changed, 1 insertions, 0 deletions
diff --git a/Sil/Syntax.dcl b/Sil/Syntax.dcl
index 58515fe..aebe32c 100644
--- a/Sil/Syntax.dcl
+++ b/Sil/Syntax.dcl
@@ -47,6 +47,7 @@ from Data.Maybe import :: Maybe
:: Op1
= Neg //* ~
+ | Not //* !
:: Op2
= Add //* +