From 407a0c8e7e14b96c2a0487cefe09cdc021f002b0 Mon Sep 17 00:00:00 2001
From: Camil Staps
Date: Wed, 19 Jul 2017 12:57:01 +0000
Subject: Add while and !, fix error in consecutive declarations

---
 Sil/Syntax.dcl | 1 +
 1 file changed, 1 insertion(+)

(limited to 'Sil/Syntax.dcl')

diff --git a/Sil/Syntax.dcl b/Sil/Syntax.dcl
index 58515fe..aebe32c 100644
--- a/Sil/Syntax.dcl
+++ b/Sil/Syntax.dcl
@@ -47,6 +47,7 @@ from Data.Maybe import :: Maybe
 
 :: Op1
 	= Neg //* ~
+	| Not //* !
 
 :: Op2
 	= Add    //* +
-- 
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