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author | Camil Staps | 2016-02-02 19:24:50 +0100 |
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committer | Camil Staps | 2016-02-02 19:24:50 +0100 |
commit | a7d7542dc646a5fd124ef71e71ce260889f1701b (patch) | |
tree | 04ed89503bbb3cc9933273a1326a53ca724c3492 /fp2/week3/mart/StdDynSet.dcl | |
parent | week6 camil: working positioning of lines by putting empties at left and righ... (diff) |
Diffstat (limited to 'fp2/week3/mart/StdDynSet.dcl')
-rw-r--r-- | fp2/week3/mart/StdDynSet.dcl | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/fp2/week3/mart/StdDynSet.dcl b/fp2/week3/mart/StdDynSet.dcl deleted file mode 100644 index de9a9b7..0000000 --- a/fp2/week3/mart/StdDynSet.dcl +++ /dev/null @@ -1,24 +0,0 @@ -definition module StdDynSet
-
-import StdOverloaded
-
-class Set a | TC, ==, toString a
-
-:: Set
-
-instance zero Set
-instance toString Set
-instance == Set
-
-toSet :: a -> Set | Set a
-
-nrOfElts :: Set -> Int
-isEmptySet :: Set -> Bool
-
-memberOfSet :: a Set -> Bool | Set a
-isSubset :: Set Set -> Bool
-isStrictSubset :: Set Set -> Bool
-
-union :: Set Set -> Set
-intersection :: Set Set -> Set
-without :: Set Set -> Set
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