diff options
| author | Camil Staps | 2016-02-02 19:24:50 +0100 |
|---|---|---|
| committer | Camil Staps | 2016-02-02 19:24:50 +0100 |
| commit | a7d7542dc646a5fd124ef71e71ce260889f1701b (patch) | |
| tree | 04ed89503bbb3cc9933273a1326a53ca724c3492 /1415/fp1/week4/mart/StdSet.dcl | |
| parent | week6 camil: working positioning of lines by putting empties at left and righ... (diff) | |
Diffstat (limited to '1415/fp1/week4/mart/StdSet.dcl')
| -rw-r--r-- | 1415/fp1/week4/mart/StdSet.dcl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/1415/fp1/week4/mart/StdSet.dcl b/1415/fp1/week4/mart/StdSet.dcl new file mode 100644 index 0000000..0c702ca --- /dev/null +++ b/1415/fp1/week4/mart/StdSet.dcl @@ -0,0 +1,25 @@ +definition module StdSet
+
+import StdClass
+
+:: Set a
+
+toSet :: [a] -> Set a | Eq a
+fromSet :: (Set a) -> [a]
+
+isEmptySet :: (Set a) -> Bool
+isDisjoint :: (Set a) (Set a) -> Bool | Eq a
+isSubset :: (Set a) (Set a) -> Bool | Eq a
+isStrictSubset :: (Set a) (Set a) -> Bool | Eq a
+memberOfSet :: a (Set a) -> Bool | Eq a
+union :: (Set a) (Set a) -> Set a | Eq a
+intersection :: (Set a) (Set a) -> Set a | Eq a
+nrOfElements :: (Set a) -> Int
+without :: (Set a) (Set a) -> Set a | Eq a
+
+product :: (Set a) (Set b) -> Set (a,b)
+
+instance zero (Set a)
+instance == (Set a) | Eq a
+
+powerSet :: (Set a) -> Set (Set a) | Eq a
|