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Diffstat (limited to 'assignment-2/serialize2start.icl')
| -rw-r--r-- | assignment-2/serialize2start.icl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/assignment-2/serialize2start.icl b/assignment-2/serialize2start.icl index d8b5ccc..3717b9c 100644 --- a/assignment-2/serialize2start.icl +++ b/assignment-2/serialize2start.icl @@ -4,6 +4,9 @@ module serialize2start Definition for assignment 2 in AFP 2017
Pieter Koopman pieter@cs.ru.nl
September 2017
+
+ Laurens Kuiper (s4467299)
+ Camil Staps (s4498062)
*/
import StdEnv, StdMaybe
@@ -132,6 +135,16 @@ where Nothing -> case read r of
Just (x,r) -> Just (RIGHT x,r)
Nothing -> Nothing
+ // This goes wrong if the two type variables of EITHER are equal (and
+ // hence read for LEFT is the same as read for RIGHT: we will always
+ // return a LEFT. Therefore, given a type
+ //
+ // :: T = C1 Int | C2 Int
+ //
+ // it is not possible to write and read C2 (C1 will be read, since LEFT
+ // has precedence). Like the example given as the answer to the
+ // reflection questin below, we don't think this to be fixable in the
+ // current setup.
instance serialize (PAIR a b) | serialize a & serialize b
where
|