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authorCamil Staps2018-01-06 15:01:50 +0100
committerCamil Staps2018-01-06 15:03:15 +0100
commitea3b84e6ce2ceafb28f82f9e3e1f725eb9f6633c (patch)
treeb8706f5b95b22d437c3692036691ee84b75e1db6 /assignment-13/uFPL.dcl
parentContinue simulator (diff)
Add RO to iTasks simulator
Diffstat (limited to 'assignment-13/uFPL.dcl')
-rw-r--r--assignment-13/uFPL.dcl3
1 files changed, 2 insertions, 1 deletions
diff --git a/assignment-13/uFPL.dcl b/assignment-13/uFPL.dcl
index 1ce2ac4..c061119 100644
--- a/assignment-13/uFPL.dcl
+++ b/assignment-13/uFPL.dcl
@@ -8,11 +8,12 @@ from uFPL.C import :: CType, :: CExpr, :: CBody, :: CVar, :: CFun, :: CProg
:: RO = RO
:: RW = RW
-:: UShared t w =
+:: UShared t rw =
{ sname :: String
, stype :: CType
, sinit :: t
, srepr :: Bimap t CExpr
+ , srw :: rw // to be able to check this in uFPL.Sim
}
:: Shares