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Diffstat (limited to 'thesis/code-addresses.tex')
| -rw-r--r-- | thesis/code-addresses.tex | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/thesis/code-addresses.tex b/thesis/code-addresses.tex index 2c3a043..4dc7338 100644 --- a/thesis/code-addresses.tex +++ b/thesis/code-addresses.tex @@ -20,7 +20,7 @@ When the LSB is set, it switches to Thumb mode~\parencite[A2.3.2]{armv7ar}. The fact that in ARM mode the two lowest bits of a value written to the PC are cleared automatically has been exploited in the ARM code generator: these two bits are used to store information. Bit 1 is used to mark a node as having reached head normal form% - \footnote{A node is in \emph{head} or \emph{root normal form} when it cannot be rewritten itself (though its children may)}. + \footnote{A node is in \emph{head} or \emph{root normal form} when it cannot be rewritten itself (though its children may).}. Bit 0 is used in Clean's default garbage collector, the copying collector, to record whether a node has been copied to the other semispace already: when cleared (the normal state of an address as stored on the heap), it has not been copied yet. @@ -49,21 +49,21 @@ Flipping the meaning of the LSB in the garbage collector amounts to swapping \ua By word-aligning all node entry addresses we lose one alignment byte per node entry address on average (assuming that half of the node entry points are word-aligned already). This increases code size slightly, but since many instructions that were 32-bit in ARM are now 16-bit, the overall code size is still smaller. -Aligning node entries has no effect on the program's efficiency, since the \ual{nop} instruction that is inserted above it will never be executed. +Aligning node entries has no effect on the program's efficiency, since the \ual{nop} instruction that is inserted above the entry is never executed. \subsection{Other solutions} \label{sec:code-addresses:other-solutions} -The solution described above exploits the fact that the LSB of a code address is only used inside the garbage collector, - and has a fixed value everywhere else. +The solution described above is Clean-specific, + since it exploits the fact that bit 0 of a code address is only used inside the garbage collector. The solution for bit 1, however, is not specific to the Clean RTS. Therefore, a general solution to the problem that the two LSBs of a code address cannot be used to store information in Thumb mode would be to align all addresses that we need to store info of on double-words, that is, ensuring the three LSBs are always zero. That way, the LSB can be used for ARM and Thumb interworking, and bit 1 and 2 can be used to store information. -Of course, whether this is a viable solution depends on the density of code addresses that should be aligned. -If every second instruction needs to be aligned, it would introduce so many \ual{nop} instructions +Of course, whether this is a viable solution depends on the density of code addresses that should then be aligned. +If every second instruction needs to be aligned, it would introduce so many padding instructions that code size will increase dramatically (even compared to ARM) and - that performance is degraded significantly. + that performance degrades significantly. Then again, in many programs the issue we have explored in this section will not be a problem at all, because the two LSBs of code addresses are not commonly used. |