Added other solutions for two-bits; moved other solutions to after comparison

1 files changed, 17 insertions, 0 deletions

diff --git a/thesis/two-bits.tex b/thesis/two-bits.tex
index 56e7c45..ac8419b 100644
--- a/thesis/two-bits.tex
+++ b/thesis/two-bits.tex
@@ -51,4 +51,21 @@ By word-aligning all node entry addresses we lose one alignment byte per node en
 This increases code size slightly, but since many instructions that were 32-bit in ARM are now 16-bit, the overall code size is still smaller.
 Aligning node entries has no effect on the program's efficiency, since the \ual{nop} instruction that is inserted above it will never be executed.
 
+\subsection{Other solutions}
+\label{sec:two-bits:other-solutions}
+The solution described above exploits the fact that the LSB of a code address is only used inside the garbage collector,
+	and has a fixed value everywhere else.
+The solution for bit 1, however, is not specific to the Clean RTS.
+Therefore, a general solution to the problem that the two LSBs of a code address cannot be used to store information in Thumb mode would be to align all addresses that we need to store info of on double-words,
+	that is, ensuring the three LSBs are always zero.
+That way, the LSB can be used for ARM and Thumb interworking, and bit 1 and 2 can be used to store information.
+
+Of course, whether this is a viable solution depends on the density of code addresses that should be aligned.
+If every second instruction needs to be aligned, it would introduce so many \ual{nop} instructions
+	that code size will increase dramatically (even compared to ARM) and
+	that performance is degraded significantly.
+
+Then again, in many programs the issue we have explored in this section will not be a problem at all,
+	because the two LSBs of code addresses are not commonly used.
+
 \end{multicols}