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authorCamil Staps2016-10-02 14:21:27 +0200
committerCamil Staps2016-10-02 18:58:32 +0200
commit1d4ac7425c4c2d9c2b1ae3bb26276b14957c5a96 (patch)
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parentTypesetting (diff)
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@@ -87,3 +87,59 @@ Started working on the actual text: wrote about
- Approach: why no ARM/Thumb-2 interworking
- Difficulties with storing the program counter
+
+### 2016-10-01
+
+**Note**: in ABC code:
+
+- `.d 1 0`: *demands* 1 argument on A-stack, 0 on B-stack
+- `.o 0 1 i`: *offers* 0 arguments on A-stack, 1 on B-stack with type `Int`
+
+**Problem**: instructions like `ldr pc,[sp],#4`. On the stack, program memory
+addresses. We need to jump to an address like that *+1* to stay in Thumb mode.
+
+Assuming every address that is stores somewhere is used like this, it is most
+efficient to fix this when storing the address rather than when loading it
+(since an address stored once may be loaded multiple times).
+
+The code generator should be adapted in `w_as_descriptor` to add 1, however,
+the same function is used to load pointers to data.
+
+### 2016-10-02
+
+**Problem**: the problem with storing the program counter was not properly
+fixed. In fact, it looks like the only reason it worked was some old binaries
+hanging around on the disk.
+
+The issue probably (**Question** for John) stems from the fact that the lowest
+two bits of addresses are used by the garbage collector and to store the
+evaluation status (evaluated or not / RNF or not, not sure). Hence, storing an
+address with offset `#9` modifies the evaluation / garbage collector
+information, giving incorrect results when using an up-to-date `_system.o`.
+
+**Solution**: the new solution is to store addresses with an offset of `#8`,
+and when jumping to an address making sure that the LSB is set (to force Thumb
+state). Hence, where we first had:
+
+```armasm
+ldr pc,[sp],#4
+```
+
+We now have:
+
+```armasm
+ldr lr,[sp],#4 @ use lr as auxiliary register
+orr lr,lr,#1 @ pc cannot be left operand of orr, so orr pc,lr,#1 is not possible
+mov pc,lr
+```
+
+Hence, not only storing addresses is slowed down by two instructions, now also
+loading addresses is slowed down by two instructions.
+
+**Question** for Rinus: the solution for this problem was influenced by the
+fact that the Clean code generator uses the lowest two bits already. If this
+weren't the case, it would be more efficient to store a `#9` offset and not
+modify addresses when jumping. What solution should be given in the thesis?
+Both?
+
+**Current commits**: cg `5effb5b`, rts `0f7f68d`, tests `f7f261f`.