summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorCamil Staps2016-11-28 22:36:50 +0100
committerCamil Staps2016-11-28 22:36:50 +0100
commit256077e79bb1ab484a5d14f3618d5ca87ae04030 (patch)
tree833aa2883715d580e097d61e107e08a9373b6edc
parentlog (diff)
log
-rw-r--r--log.md53
1 files changed, 53 insertions, 0 deletions
diff --git a/log.md b/log.md
index 69106d8..a91fe61 100644
--- a/log.md
+++ b/log.md
@@ -495,3 +495,56 @@ in cg `4290310`).
Tried compiling the Clean compiler with a hacked clm. Had to `strip cocl`
manually, then achieved a size of 5.1M (5325412 bytes) compared to 5.3M
(5475152) for ARM. Segfaults, of course, when tried to use.
+
+### 2016-11-28
+
+Hardcoded registers in `cgthumb2was.c` (not in the `register_name` array):
+
+- `r12`, r. 601, 606, 613, 619 (`w_as_*scratch_register*`) (removed `a24f0e1`)
+- `sp`, r. 1186 (`dyadic_instruction_allowed`, goes through `register_name`),
+ 2396 (`rts`), 2412 (`rtsi`)
+- `pc`, r. 1425, 1431 (`jmp`), 1541, 1544, 1555, 1561, 1566 (`jsr`), 2396
+ (`rts`), 2412 (`rtsi`)
+- `lr`, r. 1541, 1544, 1555, 1561, 1566 (`jsr`) (removed `a24f0e1`)
+- `r5`, r. 2750, 2762 (`garbage_collect_test`) (removed `a24f0e1`)
+
+The below table lists some options that can be looked at for the register
+allocation optimisations. The first column, ARM, is the allocation as is used
+in the ARM RTS/CG, the other columns are possible changes.
+
+| Option | ARM | +Aux, -B | +Aux, -A | +Aux, +A | Aux/B, -A | Aux/B, -Scratch | Aux/B, -Link | Aux/B, -Heap |
+|------------------|:-----:|:--------:|:--------:|:--------:|:---------:|:---------------:|:------------:|:------------:|
+| **B-stack** | **4** | **4** | **4** | 8 | **4** | **4** | **4** | **4** |
+| | **3** | 14 | **3** | 14 | **3** | **3** | **3** | **3** |
+| | **2** | 12 | **2** | 12 | 12 | 14 | 12 | 14 |
+| | **1** | 10 | 10 | 10 | 10 | 10 | 10 | 12 |
+| | **0** | 9 | 9 | 9 | 14 | 9 | 9 | 9 |
+| **A-stack** | **6** | **6** | 14 | **6** | **6** | **6** | **6** | **6** |
+| | **7** | **7** | 12 | **7** | **7** | **7** | **7** | **7** |
+| | 8 | 8 | 8 | **4** | 8 | 8 | 8 | 8 |
+| | 11 | 11 | 11 | 11 | 11 | 11 | 11 | 11 |
+| **Free heap** | **5** | **5** | **5** | **5** | **5** | **5** | **5** | **5** |
+| **A ptr** | 9 | **0** | **0** | **0** | 9 | **0** | **0** | **0** |
+| **Heap ptr** | 10 | **1** | **1** | **1** | **1** | **1** | **1** | 10 |
+| **Scratch** | 12 | **2** | **7** | **2** | **2** | 12 | **2** | **1** |
+| **B ptr** | 13 | 13 | 13 | 13 | 13 | 13 | 13 | 13 |
+| **Link/Scratch** | 14 | **3** | **6** | **3** | **0** | **2** | 14 | **2** |
+
+However, before this can be tried out, there is an **issue** in the code
+generator which makes that `frontend/predef.icl` in the cocl cannot be
+compiled: in the long array updates there are many negative offset addresses,
+and in Thumb these can be at most 255.
+
+Made some changes to the garbage collector:
+
+- In the copying collector, modified `copy_arity_0_node2_` to hopefully store
+ the right LSB (rts `5a329af`)
+- In the compacting/marking collector, there was still an issue with an address
+ being loaded from an address off-by-one (e.g. `0xcc000002f6` instead of
+ `0x2f60e`); fixed this temporarily in rts `b8710c5` but should talk to John
+ about this. Also, the compacting compiler still breaks on the following with
+ `-h 1k`:
+
+ ```clean
+ Start = (length xs, hd xs) where xs = fromto 1 100
+ ```