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authorCamil Staps2017-07-19 12:59:53 +0000
committerCamil Staps2017-07-19 12:59:53 +0000
commita8534a038f3c9588243ff5ab940e974f10f66a19 (patch)
treed3948c3b7c008f4dd03c4f98070761ad14a2e9a8
parentAdd while and !, fix error in consecutive declarations (diff)
Add while and ! to printer
-rw-r--r--Sil/Syntax.icl1
-rw-r--r--Sil/Util/Printer.icl2
2 files changed, 3 insertions, 0 deletions
diff --git a/Sil/Syntax.icl b/Sil/Syntax.icl
index c812508..0056618 100644
--- a/Sil/Syntax.icl
+++ b/Sil/Syntax.icl
@@ -37,6 +37,7 @@ where
instance toString Op1
where
toString Neg = "~"
+ toString Not = "!"
instance toString Op2
where
diff --git a/Sil/Util/Printer.icl b/Sil/Util/Printer.icl
index af3d072..d35281b 100644
--- a/Sil/Util/Printer.icl
+++ b/Sil/Util/Printer.icl
@@ -98,6 +98,8 @@ where
else` = case else of
Nothing -> ""
Just e -> " else {\r\n" <+ print st` e <+ "\r\n" <+ st <+ "}"
+ print st (While c do) = st <+ "while (" <+ c <+ ") {\r\n" <+
+ print (incIndent st) do <+ "\r\n" <+ st <+ "}"
print st stm = st <+ stm
printersperse :: a [b] -> String | toString a & toString b