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authorCamil Staps2016-06-23 14:47:40 +0200
committerCamil Staps2016-06-23 14:47:40 +0200
commit3019b3684d0d94f318f719bfdd5163e84d9e91b0 (patch)
treeb59d85d07c548024669300eca6dd56ad9113d02e /doc/comp.tex
parentInitial commit (diff)
Update instruction setHEADmaster
Diffstat (limited to 'doc/comp.tex')
-rw-r--r--doc/comp.tex4
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/comp.tex b/doc/comp.tex
index 70dc2e5..c3c1f74 100644
--- a/doc/comp.tex
+++ b/doc/comp.tex
@@ -3,7 +3,7 @@ Our chip consists of the following static components:
\begin{itemize}
\item An ALU: $\ALUOp \times \Word8 \times \Word8 \to \Word8$.
- \item The program memory $\prog$: $\Prog \eqdef \Word6^{256}$.
+ \item The program memory $\prog$: $\Prog \eqdef \Word4^{256}$.
\end{itemize}
And these volatile components:
@@ -25,5 +25,5 @@ And these volatile components:
\end{itemize}
A state $\st$ can be seen as a tuple $(\prog,\mem)$. We define the set of all
-states $\State \eqdef \Word6^{256} \times \Word8^{256}$. An instruction is a
+states $\State \eqdef \Word4^{256} \times \Word8^{256}$. An instruction is a
function $\Mem\to\Mem$. The instruction cycle is a function $\State\to\State$.