diff options
Diffstat (limited to 'firmware/init.c')
-rw-r--r-- | firmware/init.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/firmware/init.c b/firmware/init.c new file mode 100644 index 0000000..04e27a6 --- /dev/null +++ b/firmware/init.c @@ -0,0 +1,73 @@ +#include <xc.h> + +#include "t6963c_specific.h" +#include "t6963c/t6963c.h" + +void init_clock(void) { + // CPDIV 1:1; RCDIV FRC/2; DOZE 1:8; G1CLKSEL disabled; DOZEN disabled; ROI disabled; + CLKDIV = 0x3100; + // GCLKDIV 1; + CLKDIV2 = 0x0000; +} + +void init_pins(void) { + LATB = 0x00; + TRISB = 0xFFFF; + LATC = 0x00; + TRISC = 0xF000; + LATD = 0x00; + TRISD = 0x0AFF; + LATE = 0x00; + TRISE = 0xFF; + LATF = 0x00; + TRISF = 0xBB; + LATG = 0x00; + TRISG = 0x038C; + + /**************************************************************************** + * Setting the Analog/Digital Configuration SFR + ***************************************************************************/ + ANSB = 0x3F; + ANSC = 0x6000; + ANSD = 0xC0; + ANSF = 0x01; + ANSG = 0x00; + + /**************************************************************************** + * Set the PPS + ***************************************************************************/ + __builtin_write_OSCCONL(OSCCON & 0xbf); // unlock PPS + RPOR1bits.RP2R = 0x03; // RD8->UART1:U1TX + RPINR18bits.U1RXR = 0x04; // RD9->UART1:U1RX + RPOR1bits.RP3R = 0x04; // RD10->UART1:U1RTS + RPINR18bits.U1CTSR = 0x0C; // RD11->UART1:U1CTS + RPOR10bits.RP21R = 0x07; // RG6->SPI1:SDO1 + RPINR20bits.SDI1R = 0x1A; // RG7->SPI1:SDI1 + RPOR9bits.RP19R = 0x08; // RG8->SPI1:SCK1OUT + RPOR13bits.RP27R = 0x09; // RG9->SPI1:SS1OUT + __builtin_write_OSCCONL(OSCCON | 0x40); // lock PPS +} + +void init_lcd(void) { + t6963c_init(); + t6963c_clear(); +} + +void init_uart(void) { + // STSEL 1; IREN disabled; PDSEL 8N; UARTEN enabled; RTSMD disabled; RXINV disabled; USIDL disabled; WAKE disabled; ABAUD disabled; LPBACK disabled; BRGH enabled; UEN TX_RX; + U1MODE = 0x8008; + // OERR NO_ERROR_cleared; UTXISEL0 TX_ONE_CHAR; URXISEL RX_ONE_CHAR; UTXBRK COMPLETED; UTXEN disabled; ADDEN disabled; UTXINV disabled; + U1STA = 0x0000; + // U1TXREG 0x0000; + U1TXREG = 0x0000; + // U1RXREG 0x0000; + U1RXREG = 0x0000; + // Baud Rate = 115200; BRG 34; + U1BRG = 0x0022; +} + +void init(void) { + init_clock(); + init_pins(); + init_lcd(); +} |