.include "thumb2regs.s" .arch armv7-a .syntax unified .thumb .fpu vfpv3-d16 .text .globl divide .thumb_func .align divide: eor SCRATCH_REG,BSTACK_1,BSTACK_0 cmp BSTACK_0,#0 it lt neglt BSTACK_0,BSTACK_0 cmp BSTACK_1,#0 it lt neglt BSTACK_1,BSTACK_1 cmp BSTACK_0,#32 bls divide_by_small_number clz BSTACK_3,BSTACK_0 clz BSTACK_2,BSTACK_1 rsb BSTACK_3,BSTACK_3,#31-5-11 add BSTACK_3,BSTACK_3,BSTACK_2 mov BSTACK_2,#0 cmp BSTACK_3,#32-5-11 bhs divide_large_result add BSTACK_3,BSTACK_3,BSTACK_3,lsl #1 .align @ alignment is right now, try to not make this a nop add LINK_REG,pc,#6 add LINK_REG,LINK_REG,BSTACK_3,lsl #2 mov pc,LINK_REG .set shift,32-5-11 .rept 32-5-11 .set shift,shift-1 subs BSTACK_3,BSTACK_1,BSTACK_0,lsl #shift itt cs movcs BSTACK_1,BSTACK_3 orrcs BSTACK_2,BSTACK_2,#1<