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-rw-r--r--cgaas.c217
-rw-r--r--cgas.c2
-rw-r--r--cgawas.c271
-rw-r--r--cgcalc.c123
-rw-r--r--cgcode.c379
-rw-r--r--cgcodep.h3
-rw-r--r--cgconst.h8
-rw-r--r--cgias.c86
-rw-r--r--cgiconst.h5
-rw-r--r--cginput.c3
-rw-r--r--cginstructions.c86
-rw-r--r--cginstructions.h12
-rw-r--r--cgiwas.c56
-rw-r--r--cglin.c524
-rw-r--r--cgopt.c27
-rw-r--r--cgpas.c84
-rw-r--r--cgpwas.c2
-rw-r--r--cgsas.c2
-rw-r--r--cgswas.c2
-rw-r--r--cgwas.c2
20 files changed, 1632 insertions, 262 deletions
diff --git a/cgaas.c b/cgaas.c
index 5e9bb02..11ba458 100644
--- a/cgaas.c
+++ b/cgaas.c
@@ -1718,7 +1718,7 @@ static void as_moveb_instruction (struct instruction *instruction)
internal_error_in_function ("as_moveb_instruction");
}
-static void as_movew_instruction (struct instruction *instruction)
+static void as_movedb_instruction (struct instruction *instruction)
{
switch (instruction->instruction_parameters[1].parameter_type){
case P_REGISTER:
@@ -1763,10 +1763,135 @@ static void as_movew_instruction (struct instruction *instruction)
break;
}
}
- internal_error_in_function ("as_movew_instruction");
+ internal_error_in_function ("as_movedb_instruction");
}
-static void as_movesw_instruction (struct instruction *instruction)
+static void as_moveqb_instruction (struct instruction *instruction)
+{
+ switch (instruction->instruction_parameters[1].parameter_type){
+ case P_REGISTER:
+ {
+ int reg;
+
+ reg=instruction->instruction_parameters[1].parameter_data.reg.r;
+ switch (instruction->instruction_parameters[0].parameter_type){
+ case P_REGISTER:
+ as_br_br (0213,instruction->instruction_parameters[0].parameter_data.reg.r,reg);
+ return;
+ case P_IMMEDIATE:
+ {
+ int reg_n;
+
+ reg_n=reg_num (reg);
+ if (reg_n>=4)
+ store_c (0x40 | ((reg_n & 8)>>3));
+ store_c (0270 | (reg_n & 7));
+ store_l (instruction->instruction_parameters[0].parameter_data.i);
+ return;
+ }
+ }
+
+ break;
+ }
+ case P_INDIRECT:
+ switch (instruction->instruction_parameters[0].parameter_type){
+ case P_IMMEDIATE:
+ {
+ int reg1,reg1_n,offset;
+
+ offset=instruction->instruction_parameters[1].parameter_offset;
+ reg1=instruction->instruction_parameters[1].parameter_data.reg.r;
+
+ reg1_n=reg_num (reg1);
+
+ if (reg1_n & 8)
+ store_c (0x41);
+ store_c (0307);
+ if ((reg1_n & 7)==4/*RSP or R12*/){
+ if (offset==0){
+ store_c (0x04);
+ store_c (0044);
+ } else if (((signed char)offset)==offset){
+ store_c (0x44);
+ store_c (0044);
+ store_c (offset);
+ } else {
+ store_c (0x84);
+ store_c (0044);
+ store_l (offset);
+ }
+ } else {
+ if (offset==0 && (reg1_n & 7)!=5/*RBP or R13*/){
+ store_c (reg1_n & 7);
+ } else if (((signed char)offset)==offset){
+ store_c (0x40 | (reg1_n & 7));
+ store_c (offset);
+ } else {
+ store_c (0x80 | (reg1_n & 7));
+ store_l (offset);
+ }
+ }
+ store_l (instruction->instruction_parameters[0].parameter_data.i);
+ return;
+ }
+ case P_REGISTER:
+ as_br_id (0211,instruction->instruction_parameters[0].parameter_data.reg.r,
+ instruction->instruction_parameters[1].parameter_offset,
+ instruction->instruction_parameters[1].parameter_data.reg.r);
+ return;
+ }
+ break;
+ case P_INDEXED:
+ switch (instruction->instruction_parameters[0].parameter_type){
+ case P_IMMEDIATE:
+ {
+ int reg1,reg2,reg1_n,reg2_n,shift,offset,x;
+
+ offset=instruction->instruction_parameters[1].parameter_offset;
+ reg1=instruction->instruction_parameters[1].parameter_data.ir->a_reg.r;
+ reg2=instruction->instruction_parameters[1].parameter_data.ir->d_reg.r;
+
+ reg1_n=reg_num (reg1);
+ reg2_n=reg_num (reg2);
+
+ shift=offset & 3;
+ offset=offset>>2;
+
+ if (reg2==ESP)
+ internal_error_in_function ("as_moveqb_instruction");
+
+ if (((reg1_n | reg2_n) & 8)!=0)
+ store_c (0x40 | ((reg2_n & 8)>>2) | ((reg1_n & 8)>>3));
+ store_c (0307);
+ x=(shift<<6) | ((reg2_n & 7)<<3) | (reg1_n & 7);
+ if (offset==0 && (reg1_n & 7)!=5/*RBP or R13*/){
+ store_c (0x04);
+ store_c (x);
+ } else if (((signed char)offset)==offset){
+ store_c (0x44);
+ store_c (x);
+ store_c (offset);
+ } else {
+ store_c (0x84);
+ store_c (x);
+ store_l (offset);
+ }
+ store_l (instruction->instruction_parameters[0].parameter_data.i);
+
+ return;
+ }
+ case P_REGISTER:
+ as_br_x (0211,instruction->instruction_parameters[0].parameter_data.reg.r,
+ instruction->instruction_parameters[1].parameter_offset,
+ instruction->instruction_parameters[1].parameter_data.ir);
+ return;
+ }
+ break;
+ }
+ internal_error_in_function ("as_moveqb_instruction");
+}
+
+static void as_loadsqb_instruction (struct instruction *instruction)
{
switch (instruction->instruction_parameters[1].parameter_type){
case P_REGISTER:
@@ -1788,7 +1913,7 @@ static void as_movesw_instruction (struct instruction *instruction)
break;
}
}
- internal_error_in_function ("as_movesw_instruction");
+ internal_error_in_function ("as_loadsqb_instruction");
}
static void as_lea_instruction (struct instruction *instruction)
@@ -3464,6 +3589,11 @@ static void as_f_i (int code1,int code2,DOUBLE *r_p,int d_freg)
new_label->label_flags=DATA_LABEL;
+#ifdef FUNCTION_LEVEL_LINKING
+ if (data_object_label==NULL)
+ as_new_data_module();
+#endif
+
if (data_object_label->object_section_align<3)
data_object_label->object_section_align=3;
if ((data_buffer_p-current_data_buffer->data-data_object_label->object_label_offset) & 4)
@@ -3520,6 +3650,53 @@ static void as_fmove_instruction (struct instruction *instruction)
internal_error_in_function ("as_fmove_instruction");
}
+static void as_floads_instruction (struct instruction *instruction)
+{
+ switch (instruction->instruction_parameters[1].parameter_type){
+ case P_F_REGISTER:
+ switch (instruction->instruction_parameters[0].parameter_type){
+ case P_INDIRECT:
+ /* cvtss2sd */
+ as_f_id (0xf3,0x5a,instruction->instruction_parameters[0].parameter_offset,
+ instruction->instruction_parameters[0].parameter_data.reg.r,
+ instruction->instruction_parameters[1].parameter_data.reg.r);
+ return;
+ case P_INDEXED:
+ /* cvtss2sd */
+ as_f_x (0xf3,0x5a,instruction->instruction_parameters[0].parameter_offset,
+ instruction->instruction_parameters[0].parameter_data.ir,
+ instruction->instruction_parameters[1].parameter_data.reg.r);
+ return;
+ }
+ break;
+ }
+ internal_error_in_function ("as_floads_instruction");
+}
+
+static void as_fmoves_instruction (struct instruction *instruction)
+{
+ switch (instruction->instruction_parameters[1].parameter_type){
+ case P_INDIRECT:
+ if (instruction->instruction_parameters[0].parameter_type==P_F_REGISTER){
+ /* movss */
+ as_f_id (0xf3,0x11,instruction->instruction_parameters[1].parameter_offset,
+ instruction->instruction_parameters[1].parameter_data.reg.r,
+ instruction->instruction_parameters[0].parameter_data.reg.r);
+ return;
+ }
+ break;
+ case P_INDEXED:
+ if (instruction->instruction_parameters[0].parameter_type==P_F_REGISTER){
+ /* movsd */
+ as_f_x (0xf3,0x11,instruction->instruction_parameters[1].parameter_offset,
+ instruction->instruction_parameters[1].parameter_data.ir,
+ instruction->instruction_parameters[0].parameter_data.reg.r);
+ return;
+ }
+ }
+ internal_error_in_function ("as_fmoves_instruction");
+}
+
static void as_dyadic_float_instruction (struct instruction *instruction,int code1,int code2)
{
int d_freg;
@@ -3583,6 +3760,11 @@ static void as_float_neg_instruction (struct instruction *instruction)
new_label->label_flags=DATA_LABEL;
+#ifdef FUNCTION_LEVEL_LINKING
+ if (data_object_label==NULL)
+ as_new_data_module();
+#endif
+
if (data_object_label->object_section_align<4)
data_object_label->object_section_align=4;
while ((data_buffer_p-current_data_buffer->data-data_object_label->object_label_offset) & 0xc)
@@ -3636,6 +3818,11 @@ static void as_float_abs_instruction (struct instruction *instruction)
new_label->label_flags=DATA_LABEL;
+#ifdef FUNCTION_LEVEL_LINKING
+ if (data_object_label==NULL)
+ as_new_data_module();
+#endif
+
if (data_object_label->object_section_align<4)
data_object_label->object_section_align=4;
while ((data_buffer_p-current_data_buffer->data-data_object_label->object_label_offset) & 0xc)
@@ -4121,15 +4308,18 @@ static void as_instructions (struct instruction *instruction)
case IBTST:
as_btst_instruction (instruction);
break;
- case IMOVEW:
- as_movew_instruction (instruction);
- break;
- case IMOVESW:
- as_movesw_instruction (instruction);
+ case ILOADSQB:
+ as_loadsqb_instruction (instruction);
break;
case IMOVEB:
as_moveb_instruction (instruction);
break;
+ case IMOVEDB:
+ as_movedb_instruction (instruction);
+ break;
+ case IMOVEQB:
+ as_moveqb_instruction (instruction);
+ break;
case IEXG:
as_exg_instruction (instruction);
break;
@@ -4220,6 +4410,15 @@ static void as_instructions (struct instruction *instruction)
case IFSNE:
as_set_float_condition_instruction (instruction,3);
break;
+ case IFLOADS:
+ as_floads_instruction (instruction);
+ break;
+ case IFCVT2S:
+ as_dyadic_float_instruction (instruction,0xf2,0x5a); /* cvtsd2ss */
+ break;
+ case IFMOVES:
+ as_fmoves_instruction (instruction);
+ break;
case IRTSI:
as_rtsi_instruction (instruction);
break;
diff --git a/cgas.c b/cgas.c
index 5e6cc27..7dc8b79 100644
--- a/cgas.c
+++ b/cgas.c
@@ -3416,7 +3416,7 @@ static void write_instructions (struct instruction *instructions)
case IMOVEM:
as_movem_instruction (instruction);
break;
- case IMOVEW:
+ case IMOVEDB:
as_move_instruction (instruction,SIZE_WORD);
break;
case IMOVEB:
diff --git a/cgawas.c b/cgawas.c
index 288a26e..bf9ece6 100644
--- a/cgawas.c
+++ b/cgawas.c
@@ -367,7 +367,7 @@ void w_as_descriptor_string_in_data_section (char *string,int length,int string_
w_as_newline();
}
-enum { SIZE_LONG, SIZE_WORD, SIZE_BYTE };
+enum { SIZE_OBYTE, SIZE_QBYTE, SIZE_DBYTE, SIZE_BYTE, };
static void w_as_label (char *label)
{
@@ -488,6 +488,12 @@ static char register_name_char2[16]="piip xxxx012345";
static char *byte_register_name[16]= {"spl","dil","sil","bpl","r9b","r8b","dl","cl","al","bl",
"r10b","r11b","r12b","r13b","r14b","r15b"};
+static char *dbyte_register_name[16]= {"sp","di","si","bp","r9w","r8w","dx","cx","ax","bx",
+ "r10w","r11w","r12w","r13w","r14w","r15w"};
+
+static char *qbyte_register_name[16]= {"esp","edi","esi","ebp","r9l","r8l","edx","ecx","eax","ebx",
+ "r10l","r11l","r12l","r13l","r14l","r15l"};
+
#define REGISTER_O0 (-5)
#define REGISTER_R8 (-3)
#define REGISTER_R9 (-4)
@@ -750,6 +756,17 @@ static void w_as_comma_byte_register (int reg)
w_as_byte_register (reg);
}
+static void w_as_qbyte_register (int reg)
+{
+ fprintf (assembly_file,"%s",qbyte_register_name[reg+8]);
+}
+
+static void w_as_comma_qbyte_register (int reg)
+{
+ w_as_comma();
+ w_as_qbyte_register (reg);
+}
+
static void w_as_call_or_jump (struct parameter *parameter,char *opcode)
{
switch (parameter->parameter_type){
@@ -853,8 +870,12 @@ static void w_as_opcode_movl (void)
static void w_as_opcode_move (int size_flag)
{
- w_as_opcode (intel_asm ? (size_flag==SIZE_LONG ? "mov" : size_flag==SIZE_WORD ? "movsx" : "movzx")
- : (size_flag==SIZE_LONG ? "movl" : size_flag==SIZE_WORD ? "movswl" : "movzbl")
+ w_as_opcode (intel_asm ? (size_flag==SIZE_OBYTE ? "mov" :
+ size_flag==SIZE_BYTE ? "movzx" :
+ size_flag==SIZE_DBYTE ? "movsx" : "movsxd")
+ : (size_flag==SIZE_OBYTE ? "movl" :
+ size_flag==SIZE_BYTE ? "movzbl" :
+ size_flag==SIZE_DBYTE ? "movswl" : "movsxd")
);
}
@@ -899,6 +920,20 @@ static void w_as_immediate_register_newline (int_64 i,int reg)
w_as_newline();
}
+static void print_ptr (int size_flag)
+{
+ char *s;
+
+ switch (size_flag){
+ case SIZE_BYTE: s="byte ptr "; break;
+ case SIZE_DBYTE: s="word ptr "; break;
+ case SIZE_QBYTE: s="dword ptr "; break;
+ case SIZE_OBYTE: s="qword ptr "; break;
+ default: return;
+ }
+ fprintf (assembly_file,s);
+}
+
static void w_as_move_instruction (struct instruction *instruction,int size_flag)
{
switch (instruction->instruction_parameters[1].parameter_type){
@@ -932,8 +967,8 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
w_as_opcode_move (size_flag);
if (intel_asm){
w_as_register_comma (instruction->instruction_parameters[1].parameter_data.reg.r);
- if (size_flag!=SIZE_LONG)
- fprintf (assembly_file,size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ if (size_flag!=SIZE_OBYTE)
+ print_ptr (size_flag);
}
w_as_indirect (instruction->instruction_parameters[0].parameter_offset,
instruction->instruction_parameters[0].parameter_data.reg.r);
@@ -942,8 +977,8 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
w_as_opcode_move (size_flag);
if (intel_asm){
w_as_register_comma (instruction->instruction_parameters[1].parameter_data.reg.r);
- if (size_flag!=SIZE_LONG)
- fprintf (assembly_file,size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ if (size_flag!=SIZE_OBYTE)
+ print_ptr (size_flag);
}
w_as_indexed (instruction->instruction_parameters[0].parameter_offset,
instruction->instruction_parameters[0].parameter_data.ir);
@@ -989,8 +1024,8 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
w_as_opcode_move (size_flag);
if (intel_asm){
w_as_scratch_register_comma();
- if (size_flag!=SIZE_LONG)
- fprintf (assembly_file,size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ if (size_flag!=SIZE_OBYTE)
+ print_ptr (size_flag);
}
w_as_indirect (parameter.parameter_offset,parameter.parameter_data.reg.r);
if (!intel_asm)
@@ -1004,8 +1039,8 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
w_as_opcode_move (size_flag);
if (intel_asm){
w_as_scratch_register_comma();
- if (size_flag!=SIZE_LONG)
- fprintf (assembly_file,size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ if (size_flag!=SIZE_OBYTE)
+ print_ptr (size_flag);
}
w_as_indexed (parameter.parameter_offset,parameter.parameter_data.ir);
if (!intel_asm)
@@ -1029,7 +1064,7 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
#else
w_as_opcode_movl();
if (intel_asm){
- fprintf (assembly_file,size_flag==SIZE_LONG ? "qword ptr " : size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ print_ptr (size_flag);
w_as_indirect (instruction->instruction_parameters[1].parameter_offset,
instruction->instruction_parameters[1].parameter_data.reg.r);
w_as_comma();
@@ -1069,51 +1104,27 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
internal_error_in_function ("w_as_move");
}
- if (size_flag==SIZE_BYTE && parameter.parameter_type==P_REGISTER && parameter.parameter_data.reg.r<REGISTER_A1){
- int reg,reg1;
-
- reg=parameter.parameter_data.reg.r;
-
- w_as_opcode_register_register_newline ("xchg",reg,REGISTER_D0);
-
- reg1=instruction->instruction_parameters[1].parameter_data.reg.r;
- if (reg1==reg)
- reg1=REGISTER_D0;
- else if (reg1==REGISTER_D0)
- reg1=reg;
-
- w_as_opcode (intel_asm ? "mov" : "movb");
- if (!intel_asm)
- w_as_register_comma (REGISTER_D0);
- w_as_indirect (instruction->instruction_parameters[1].parameter_offset,reg1);
- if (intel_asm){
- if (parameter.parameter_type!=P_REGISTER)
- internal_error_in_function ("w_as_move_instruction");
- w_as_comma_byte_register (REGISTER_D0);
- }
- w_as_newline();
-
- w_as_opcode_register_register_newline ("xchg",reg,REGISTER_D0);
-
- return;
- }
-
- w_as_opcode (intel_asm ? "mov" : (size_flag==SIZE_LONG ? "movl" : size_flag==SIZE_WORD ? "movw" : "movb"));
+ w_as_opcode (intel_asm ? "mov" : (size_flag==SIZE_OBYTE ? "movq" :
+ size_flag==SIZE_BYTE ? "movb" :
+ size_flag==SIZE_DBYTE ? "movw" :"movl"));
if (!intel_asm)
w_as_parameter_comma (&parameter);
else if (parameter.parameter_type==P_IMMEDIATE)
- fprintf (assembly_file,size_flag==SIZE_LONG ? "qword ptr " : size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ print_ptr (size_flag);
w_as_indirect (instruction->instruction_parameters[1].parameter_offset,
instruction->instruction_parameters[1].parameter_data.reg.r);
if (intel_asm){
- if (size_flag==SIZE_LONG || parameter.parameter_type==P_IMMEDIATE)
- w_as_comma_parameter (&parameter);
- else if (size_flag==SIZE_WORD)
+ if (size_flag==SIZE_OBYTE || parameter.parameter_type==P_IMMEDIATE)
+ w_as_comma_parameter (&parameter);
+ else if (size_flag==SIZE_DBYTE)
w_as_comma_word_parameter (&parameter);
else {
if (parameter.parameter_type!=P_REGISTER)
internal_error_in_function ("w_as_move_instruction");
- w_as_comma_byte_register (parameter.parameter_data.reg.r);
+ if (size_flag==SIZE_BYTE)
+ w_as_comma_byte_register (parameter.parameter_data.reg.r);
+ else
+ w_as_comma_qbyte_register (parameter.parameter_data.reg.r);
}
}
w_as_newline();
@@ -1154,8 +1165,8 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
w_as_opcode_move (size_flag);
if (intel_asm){
w_as_scratch_register_comma();
- if (size_flag!=SIZE_LONG)
- fprintf (assembly_file,size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ if (size_flag!=SIZE_OBYTE)
+ print_ptr (size_flag);
}
w_as_indirect (parameter.parameter_offset,parameter.parameter_data.reg.r);
if (!intel_asm)
@@ -1206,62 +1217,25 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
internal_error_in_function ("w_as_move");
}
- if (size_flag==SIZE_BYTE && parameter.parameter_type==P_REGISTER && parameter.parameter_data.reg.r<REGISTER_A1){
- int reg,reg1,reg2;
- struct index_registers index_registers;
-
- reg=parameter.parameter_data.reg.r;
-
- w_as_opcode_register_register_newline ("xchg",reg,REGISTER_D0);
-
- reg1=instruction->instruction_parameters[1].parameter_data.ir->a_reg.r;
- reg2=instruction->instruction_parameters[1].parameter_data.ir->d_reg.r;
-
- if (reg1==reg)
- reg1=REGISTER_D0;
- else if (reg1==REGISTER_D0)
- reg1=reg;
-
- if (reg2==reg)
- reg2=REGISTER_D0;
- else if (reg2==REGISTER_D0)
- reg2=reg;
-
- index_registers.a_reg.r=reg1;
- index_registers.d_reg.r=reg2;
-
- w_as_opcode (intel_asm ? "mov" : "movb");
- if (!intel_asm)
- w_as_register_comma (REGISTER_D0);
- w_as_indexed (instruction->instruction_parameters[1].parameter_offset,&index_registers);
- if (intel_asm){
- if (parameter.parameter_type!=P_REGISTER)
- internal_error_in_function ("w_as_move_instruction");
- w_as_comma_byte_register (REGISTER_D0);
- }
- w_as_newline();
-
- w_as_opcode_register_register_newline ("xchg",reg,REGISTER_D0);
-
- return;
- }
-
- w_as_opcode (intel_asm ? "mov" : (size_flag==SIZE_LONG ? "movl" : size_flag==SIZE_WORD ? "movw" : "movb"));
+ w_as_opcode (intel_asm ? "mov" : (size_flag==SIZE_OBYTE ? "movl" : size_flag==SIZE_DBYTE ? "movw" : "movb"));
if (!intel_asm)
w_as_parameter_comma (&parameter);
else if (parameter.parameter_type==P_IMMEDIATE)
- fprintf (assembly_file,size_flag==SIZE_LONG ? "qword ptr " : size_flag==SIZE_WORD ? "word ptr " : "byte ptr ");
+ fprintf (assembly_file,size_flag==SIZE_OBYTE ? "qword ptr " : size_flag==SIZE_DBYTE ? "word ptr " : "byte ptr ");
w_as_indexed (instruction->instruction_parameters[1].parameter_offset,
instruction->instruction_parameters[1].parameter_data.ir);
if (intel_asm){
- if (size_flag==SIZE_LONG || parameter.parameter_type==P_IMMEDIATE)
- w_as_comma_parameter (&parameter);
- else if (size_flag==SIZE_WORD)
+ if (size_flag==SIZE_OBYTE || parameter.parameter_type==P_IMMEDIATE)
+ w_as_comma_parameter (&parameter);
+ else if (size_flag==SIZE_DBYTE)
w_as_comma_word_parameter (&parameter);
else {
if (parameter.parameter_type!=P_REGISTER)
internal_error_in_function ("w_as_move_instruction");
- w_as_comma_byte_register (parameter.parameter_data.reg.r);
+ if (size_flag==SIZE_BYTE)
+ w_as_comma_byte_register (parameter.parameter_data.reg.r);
+ else
+ w_as_comma_qbyte_register (parameter.parameter_data.reg.r);
}
}
w_as_newline();
@@ -1288,7 +1262,7 @@ static void w_as_move_instruction (struct instruction *instruction,int size_flag
}
}
-static void w_as_movesw_instruction (struct instruction *instruction)
+static void w_as_loadsqb_instruction (struct instruction *instruction)
{
if (instruction->instruction_parameters[1].parameter_type==P_REGISTER){
switch (instruction->instruction_parameters[0].parameter_type){
@@ -1296,7 +1270,7 @@ static void w_as_movesw_instruction (struct instruction *instruction)
w_as_opcode ("movsxd");
if (intel_asm){
w_as_register_comma (instruction->instruction_parameters[1].parameter_data.reg.r);
- fprintf (assembly_file,"word ptr ");
+ fprintf (assembly_file,"qword ptr ");
}
w_as_indirect (instruction->instruction_parameters[0].parameter_offset,
instruction->instruction_parameters[0].parameter_data.reg.r);
@@ -1305,7 +1279,7 @@ static void w_as_movesw_instruction (struct instruction *instruction)
w_as_opcode ("movsxd");
if (intel_asm){
w_as_register_comma (instruction->instruction_parameters[1].parameter_data.reg.r);
- fprintf (assembly_file,"word ptr ");
+ fprintf (assembly_file,"qword ptr ");
}
w_as_indexed (instruction->instruction_parameters[0].parameter_offset,
instruction->instruction_parameters[0].parameter_data.ir);
@@ -1317,7 +1291,7 @@ static void w_as_movesw_instruction (struct instruction *instruction)
w_as_register (instruction->instruction_parameters[0].parameter_data.reg.r);
break;
default:
- internal_error_in_function ("w_as_movesw_instruction");
+ internal_error_in_function ("w_as_loadsqb_instruction");
return;
}
if (!intel_asm)
@@ -1325,7 +1299,7 @@ static void w_as_movesw_instruction (struct instruction *instruction)
w_as_newline();
return;
}
- internal_error_in_function ("w_as_movesw_instruction");
+ internal_error_in_function ("w_as_loadsqb_instruction");
}
static void w_as_lea_instruction (struct instruction *instruction)
@@ -1591,9 +1565,9 @@ static void w_as_tst_instruction (struct instruction *instruction,int size_flag)
{
switch (instruction->instruction_parameters[0].parameter_type){
case P_INDIRECT:
- w_as_opcode (intel_asm ? "cmp" : (size_flag==SIZE_LONG ? "cmpl" : "cmpb"));
+ w_as_opcode (intel_asm ? "cmp" : (size_flag==SIZE_OBYTE ? "cmpl" : "cmpb"));
if (intel_asm){
- fprintf (assembly_file,size_flag==SIZE_LONG ? "qword ptr " : "byte ptr ");
+ fprintf (assembly_file,size_flag==SIZE_OBYTE ? "qword ptr " : "byte ptr ");
w_as_indirect (instruction->instruction_parameters[0].parameter_offset,instruction->instruction_parameters[0].parameter_data.reg.r);
w_as_comma();
}
@@ -1605,7 +1579,7 @@ static void w_as_tst_instruction (struct instruction *instruction,int size_flag)
w_as_newline();
break;
case P_INDEXED:
- w_as_opcode (intel_asm ? "cmp" : (size_flag==SIZE_LONG ? "cmpl" : "cmpb"));
+ w_as_opcode (intel_asm ? "cmp" : (size_flag==SIZE_OBYTE ? "cmpl" : "cmpb"));
if (intel_asm){
w_as_indexed (instruction->instruction_parameters[0].parameter_offset,instruction->instruction_parameters[0].parameter_data.ir);
w_as_comma();
@@ -2810,7 +2784,7 @@ static void w_as_fmove_instruction (struct instruction *instruction)
if (intel_asm)
fprintf (assembly_file,"qword ptr ");
w_as_indexed (instruction->instruction_parameters[0].parameter_offset,
- instruction->instruction_parameters[0].parameter_data.ir);
+ instruction->instruction_parameters[0].parameter_data.ir);
break;
case P_F_IMMEDIATE:
{
@@ -2859,6 +2833,69 @@ static void w_as_fmove_instruction (struct instruction *instruction)
return;
}
+static void w_as_floads_instruction (struct instruction *instruction)
+{
+ switch (instruction->instruction_parameters[1].parameter_type){
+ case P_F_REGISTER:
+ switch (instruction->instruction_parameters[0].parameter_type){
+ case P_INDIRECT:
+ w_as_opcode ("cvtss2sd");
+ w_as_fp_register (instruction->instruction_parameters[1].parameter_data.reg.r);
+ w_as_comma();
+ if (intel_asm)
+ fprintf (assembly_file,"dword ptr ");
+ w_as_indirect (instruction->instruction_parameters[0].parameter_offset,
+ instruction->instruction_parameters[0].parameter_data.reg.r);
+ break;
+ case P_INDEXED:
+ w_as_opcode ("cvtss2sd");
+ w_as_fp_register (instruction->instruction_parameters[1].parameter_data.reg.r);
+ w_as_comma();
+ if (intel_asm)
+ fprintf (assembly_file,"dword ptr ");
+ w_as_indexed (instruction->instruction_parameters[0].parameter_offset,
+ instruction->instruction_parameters[0].parameter_data.ir);
+ break;
+ default:
+ internal_error_in_function ("w_as_floads_instruction");
+ return;
+ }
+ w_as_newline();
+ return;
+ }
+ internal_error_in_function ("w_as_floads_instruction");
+ return;
+}
+
+static void w_as_fmoves_instruction (struct instruction *instruction)
+{
+ switch (instruction->instruction_parameters[1].parameter_type){
+ case P_INDIRECT:
+ case P_INDEXED:
+ if (instruction->instruction_parameters[0].parameter_type==P_F_REGISTER){
+ int s_freg;
+
+ s_freg=instruction->instruction_parameters[0].parameter_data.reg.r;
+
+ w_as_opcode ("movss");
+ if (intel_asm)
+ fprintf (assembly_file,"dword ptr ");
+ if (instruction->instruction_parameters[1].parameter_type==P_INDIRECT)
+ w_as_indirect (instruction->instruction_parameters[1].parameter_offset,
+ instruction->instruction_parameters[1].parameter_data.reg.r);
+ else
+ w_as_indexed (instruction->instruction_parameters[1].parameter_offset,
+ instruction->instruction_parameters[1].parameter_data.ir);
+
+ w_as_comma();
+ w_as_fp_register (s_freg);
+ w_as_newline();
+ return;
+ }
+ }
+ internal_error_in_function ("w_as_fmoves_instruction");
+}
+
static int int_to_real_scratch_imported=0;
static void w_as_fmovel_instruction (struct instruction *instruction)
@@ -2943,7 +2980,7 @@ static void w_as_instructions (register struct instruction *instruction)
while (instruction!=NULL){
switch (instruction->instruction_icode){
case IMOVE:
- w_as_move_instruction (instruction,SIZE_LONG);
+ w_as_move_instruction (instruction,SIZE_OBYTE);
break;
case ILEA:
w_as_lea_instruction (instruction);
@@ -3092,20 +3129,23 @@ static void w_as_instructions (register struct instruction *instruction)
break;
#endif
case ITST:
- w_as_tst_instruction (instruction,SIZE_LONG);
+ w_as_tst_instruction (instruction,SIZE_OBYTE);
break;
case IBTST:
w_as_btst_instruction (instruction);
break;
- case IMOVEW:
- w_as_move_instruction (instruction,SIZE_WORD);
- break;
- case IMOVESW:
- w_as_movesw_instruction (instruction);
+ case ILOADSQB:
+ w_as_loadsqb_instruction (instruction);
break;
case IMOVEB:
w_as_move_instruction (instruction,SIZE_BYTE);
break;
+ case IMOVEDB:
+ w_as_move_instruction (instruction,SIZE_DBYTE);
+ break;
+ case IMOVEQB:
+ w_as_move_instruction (instruction,SIZE_QBYTE);
+ break;
case IEXG:
w_as_dyadic_instruction (instruction,"xchg");
break;
@@ -3196,6 +3236,15 @@ static void w_as_instructions (register struct instruction *instruction)
case IWORD:
w_as_word_instruction (instruction);
break;
+ case IFLOADS:
+ w_as_floads_instruction (instruction);
+ break;
+ case IFCVT2S:
+ w_as_dyadic_float_instruction (instruction,"cvtsd2ss");
+ break;
+ case IFMOVES:
+ w_as_fmoves_instruction (instruction);
+ break;
case IRTSI:
w_as_rtsi_instruction (instruction);
break;
diff --git a/cgcalc.c b/cgcalc.c
index e438065..7a8de67 100644
--- a/cgcalc.c
+++ b/cgcalc.c
@@ -4,8 +4,6 @@
At: University of Nijmegen
*/
-#pragma segment Code1
-
#include <stdio.h>
#if defined (LINUX) && defined (G_AI64)
# include <stdint.h>
@@ -1410,6 +1408,9 @@ static void calculate_store_x_operator (INSTRUCTION_GRAPH graph)
switch (select_graph->instruction_code){
case GLOAD_X:
case GLOAD_B_X:
+#ifdef G_AI64
+ case GLOAD_S_X:
+#endif
if (graph_2==select_graph->instruction_parameters[0].p
/* */ && select_graph!=graph_1 /* added 18-5-1999 */
){
@@ -1437,6 +1438,9 @@ static void calculate_store_x_operator (INSTRUCTION_GRAPH graph)
select_graph=select_graph->instruction_parameters[3].p;
break;
case GFLOAD_X:
+#ifdef G_AI64
+ case GFLOAD_S_X:
+#endif
case GREGISTER:
case GFREGISTER:
select_graph=select_graph->instruction_parameters[3].p;
@@ -1753,6 +1757,9 @@ static void calculate_fstore_x_operator (INSTRUCTION_GRAPH graph)
while (select_graph!=NULL){
switch (select_graph->instruction_code){
case GFLOAD_X:
+#ifdef G_AI64
+ case GFLOAD_S_X:
+#endif
if (graph_2==select_graph->instruction_parameters[0].p){
calculate_graph_register_uses (select_graph);
@@ -1777,6 +1784,9 @@ static void calculate_fstore_x_operator (INSTRUCTION_GRAPH graph)
break;
case GLOAD_X:
case GLOAD_B_X:
+#ifdef G_AI64
+ case GLOAD_S_X:
+#endif
case GREGISTER:
case GFREGISTER:
select_graph=select_graph->instruction_parameters[3].p;
@@ -2208,6 +2218,9 @@ void calculate_graph_register_uses (INSTRUCTION_GRAPH graph)
}
case GLOAD_X:
case GLOAD_B_X:
+#ifdef G_AI64
+ case GLOAD_S_X:
+#endif
calculate_load_x_operator (graph);
return;
case GSTORE:
@@ -2245,6 +2258,9 @@ void calculate_graph_register_uses (INSTRUCTION_GRAPH graph)
}
case GSTORE_X:
case GSTORE_B_X:
+#ifdef G_AI64
+ case GSTORE_S_X:
+#endif
calculate_store_x_operator (graph);
return;
case GBEFORE:
@@ -2471,9 +2487,15 @@ void calculate_graph_register_uses (INSTRUCTION_GRAPH graph)
calculate_fstore_operator (graph);
return;
case GFLOAD_X:
+#ifdef G_AI64
+ case GFLOAD_S_X:
+#endif
calculate_fload_x_operator (graph);
return;
case GFSTORE_X:
+#ifdef G_AI64
+ case GFSTORE_S_X:
+#endif
calculate_fstore_x_operator (graph);
return;
case GFSTORE_R:
@@ -2578,7 +2600,7 @@ void calculate_graph_register_uses (INSTRUCTION_GRAPH graph)
case GRESULT1:
{
INSTRUCTION_GRAPH graph_0;
-
+
graph_0=graph->instruction_parameters[0].p;
if (graph_0->order_mode==R_NOMODE)
if (graph_0->instruction_code==GMULUD)
@@ -2601,6 +2623,56 @@ void calculate_graph_register_uses (INSTRUCTION_GRAPH graph)
return;
}
#endif
+#if defined (I486) && !defined (G_AI64)
+ case GFRESULT0:
+ case GFRESULT1:
+ {
+ INSTRUCTION_GRAPH graph_0;
+
+ graph_0=graph->instruction_parameters[0].p;
+ if (graph_0->order_mode==R_NOMODE){
+ INSTRUCTION_GRAPH graph_1;
+ int i_dregs,u_dregs;
+
+ /* GFSINCOS */
+
+ graph_1=graph_0->instruction_parameters[0].p;
+
+ calculate_graph_register_uses (graph_1);
+
+ u_dregs=graph_1->u_dregs;
+ i_dregs=graph_1->i_dregs;
+
+ graph_0->u_aregs=graph_1->u_aregs;
+ graph_0->i_aregs=graph_1->i_aregs;
+
+ if (graph_1->order_mode==R_DREGISTER)
+ i_dregs-=graph_1->order_alterable;
+ else
+ graph_0->i_aregs-=graph_1->order_alterable;
+
+ i_dregs+=2;
+
+ if (u_dregs<i_dregs)
+ u_dregs=i_dregs;
+
+ graph_0->i_dregs=i_dregs;
+ graph_0->u_dregs=u_dregs;
+
+ graph_0->order_mode=R_DREGISTER;
+ graph_0->order_alterable=0;
+ }
+
+ graph->order_mode=R_DREGISTER;
+ graph->u_aregs=graph_0->u_aregs;
+ graph->u_dregs=graph_0->u_dregs;
+ graph->i_aregs=graph_0->i_aregs;
+ graph->i_dregs=graph_0->i_dregs;
+
+ graph->order_alterable=graph->node_count<=1;
+ return;
+ }
+#endif
default:
/* printf ("%d\n",graph->instruction_code); */
internal_error_in_function ("calculate_graph_register_uses");
@@ -2732,6 +2804,11 @@ void count_graph (INSTRUCTION_GRAPH graph)
case GRESULT0:
case GRESULT1:
#endif
+#if defined (I486) && !defined (G_AI64)
+ case GFRESULT0:
+ case GFRESULT1:
+ case GFSINCOS:
+#endif
if (++graph->node_count==1)
count_graph (graph->instruction_parameters[0].p);
break;
@@ -2780,6 +2857,10 @@ void count_graph (INSTRUCTION_GRAPH graph)
case GLOAD_X:
case GLOAD_B_X:
case GFLOAD_X:
+#ifdef G_AI64
+ case GLOAD_S_X:
+ case GFLOAD_S_X:
+#endif
if (++graph->node_count==1){
count_graph (graph->instruction_parameters[0].p);
if (graph->instruction_parameters[2].p!=NULL)
@@ -2788,9 +2869,15 @@ void count_graph (INSTRUCTION_GRAPH graph)
break;
case GSTORE_X:
case GSTORE_B_X:
+#ifdef G_AI64
+ case GSTORE_S_X:
+#endif
count_gstore_x_node (graph);
break;
case GFSTORE_X:
+#ifdef G_AI64
+ case GFSTORE_S_X:
+#endif
if (++graph->node_count==1){
count_graph (graph->instruction_parameters[0].p);
count_graph (graph->instruction_parameters[1].p);
@@ -2928,6 +3015,11 @@ void mark_graph_2 (register INSTRUCTION_GRAPH graph)
case GRESULT0:
case GRESULT1:
#endif
+#if defined (I486) && !defined (G_AI64)
+ case GFRESULT0:
+ case GFRESULT1:
+ case GFSINCOS:
+#endif
if (graph->node_mark<2){
graph->node_mark=2;
mark_graph_2 (graph->instruction_parameters[0].p);
@@ -2988,6 +3080,10 @@ void mark_graph_2 (register INSTRUCTION_GRAPH graph)
case GLOAD_X:
case GLOAD_B_X:
case GFLOAD_X:
+#ifdef G_AI64
+ case GLOAD_S_X:
+ case GFLOAD_S_X:
+#endif
if (graph->node_mark<2){
graph->node_mark=2;
mark_graph_2 (graph->instruction_parameters[0].p);
@@ -2997,7 +3093,13 @@ void mark_graph_2 (register INSTRUCTION_GRAPH graph)
break;
case GSTORE_X:
case GSTORE_B_X:
+#ifdef G_AI64
+ case GSTORE_S_X:
+#endif
case GFSTORE_X:
+#ifdef G_AI64
+ case GFSTORE_S_X:
+#endif
if (graph->node_mark<2){
graph->node_mark=2;
mark_graph_2 (graph->instruction_parameters[0].p);
@@ -3133,6 +3235,11 @@ void mark_graph_1 (register INSTRUCTION_GRAPH graph)
case GRESULT0:
case GRESULT1:
#endif
+#if defined (I486) && !defined (G_AI64)
+ case GFRESULT0:
+ case GFRESULT1:
+ case GFSINCOS:
+#endif
if (!graph->node_mark){
graph->node_mark=1;
mark_graph_2 (graph->instruction_parameters[0].p);
@@ -3187,6 +3294,10 @@ void mark_graph_1 (register INSTRUCTION_GRAPH graph)
case GLOAD_X:
case GLOAD_B_X:
case GFLOAD_X:
+#ifdef G_AI64
+ case GLOAD_S_X:
+ case GFLOAD_S_X:
+#endif
if (!graph->node_mark){
graph->node_mark=1;
mark_graph_2 (graph->instruction_parameters[0].p);
@@ -3196,7 +3307,13 @@ void mark_graph_1 (register INSTRUCTION_GRAPH graph)
break;
case GSTORE_X:
case GSTORE_B_X:
+#ifdef G_AI64
+ case GSTORE_S_X:
+#endif
case GFSTORE_X:
+#ifdef G_AI64
+ case GFSTORE_S_X:
+#endif
if (!graph->node_mark){
graph->node_mark=1;
mark_graph_2 (graph->instruction_parameters[0].p);
diff --git a/cgcode.c b/cgcode.c
index 6a9305d..c8abdeb 100644
--- a/cgcode.c
+++ b/cgcode.c
@@ -224,8 +224,6 @@ int no_memory_profiling;
int no_time_profiling;
#endif
-#pragma segment Code2
-
#define g_add(g1,g2) g_instruction_2(GADD,(g1),(g2))
#define g_and(g1,g2) g_instruction_2(GAND,(g1),(g2))
#define g_asr(g1,g2) g_instruction_2(GASR,(g1),(g2))
@@ -313,6 +311,10 @@ static LABEL *halt_label,*cmp_string_label,*eqD_label,
*create_arrayB__label,*create_arrayC__label,*create_arrayI__label,*create_arrayR__label,*create_r_array__label,
*print_char_label,*print_int_label,*print_real_label;
+#ifdef G_AI64
+static LABEL *create_arrayI32_label,*create_arrayR32_label;
+#endif
+
LABEL *new_int_reducer_label,*channelP_label,*stop_reducer_label,*send_request_label,
*send_graph_label,*string_to_string_node_label,*int_array_to_node_label,
*real_array_to_node_label,*cat_string_label;
@@ -1387,6 +1389,21 @@ static void code_create_arrayI (VOID)
init_a_stack (1);
}
+#ifdef G_AI64
+static void code_create_arrayI32 (VOID)
+{
+ if (create_arrayI32_label==NULL)
+ create_arrayI32_label=enter_label ("create_arrayI32",IMPORT_LABEL);
+
+ s_push_b (s_get_b (0));
+ s_put_b (1,s_get_b (2));
+ s_put_b (2,NULL);
+ insert_basic_block (JSR_BLOCK,0,2+1,i_i_vector,create_arrayI32_label);
+
+ init_a_stack (1);
+}
+#endif
+
static void code_create_arrayR (VOID)
{
if (create_arrayR_label==NULL)
@@ -1436,6 +1453,21 @@ static void code_create_arrayR (VOID)
init_a_stack (1);
}
+#ifdef G_AI64
+static void code_create_arrayR32 (VOID)
+{
+ if (create_arrayR32_label==NULL)
+ create_arrayR32_label=enter_label ("create_arrayR32",IMPORT_LABEL);
+
+ s_push_b (s_get_b (0));
+ s_put_b (1,s_get_b (2));
+ s_put_b (2,NULL);
+ insert_basic_block (JSR_BLOCK,0,2+1,i_r_vector,create_arrayR32_label);
+
+ init_a_stack (1);
+}
+#endif
+
static void code_create_r_array (char element_descriptor[],int a_size,int b_size)
{
INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4;
@@ -1529,9 +1561,17 @@ void code_create_array (char element_descriptor[],int a_size,int b_size)
}
break;
case 'I':
- if (element_descriptor[1]=='N' && element_descriptor[2]=='T' && element_descriptor[3]=='\0'){
- code_create_arrayI();
- return;
+ if (element_descriptor[1]=='N' && element_descriptor[2]=='T'){
+ if (element_descriptor[3]=='\0'){
+ code_create_arrayI();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[3]=='3' && element_descriptor[4]=='2' && element_descriptor[5]=='\0'){
+ code_create_arrayI32();
+ return;
+ }
+#endif
}
break;
case 'P':
@@ -1541,11 +1581,17 @@ void code_create_array (char element_descriptor[],int a_size,int b_size)
}
break;
case 'R':
- if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L' &&
- element_descriptor[4]=='\0')
- {
- code_create_arrayR();
- return;
+ if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L'){
+ if (element_descriptor[4]=='\0'){
+ code_create_arrayR();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[4]=='3' && element_descriptor[5]=='2' && element_descriptor[6]=='\0'){
+ code_create_arrayR32();
+ return;
+ }
+#endif
}
break;
case 'A':
@@ -1553,7 +1599,7 @@ void code_create_array (char element_descriptor[],int a_size,int b_size)
element_descriptor[4]=='Y' && element_descriptor[5]=='\0')
{
code_create_lazy_array();
- return;
+ return;
}
break;
case 'S':
@@ -1561,19 +1607,19 @@ void code_create_array (char element_descriptor[],int a_size,int b_size)
element_descriptor[4]=='N' && element_descriptor[5]=='G' && element_descriptor[6]=='\0')
{
code_create_lazy_array();
- return;
+ return;
}
break;
case 'W':
if (is__orld (element_descriptor)){
code_create_lazy_array();
- return;
+ return;
}
break;
case '_':
if (element_descriptor[1]=='_' && element_descriptor[2]=='\0'){
code_create_lazy_array();
- return;
+ return;
}
break;
}
@@ -6080,6 +6126,39 @@ static void code_replaceI (VOID)
s_put_a (0,graph_4);
}
+#ifdef G_AI64
+static void code_replaceI32 (VOID)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4,graph_5;
+
+ graph_1=s_get_a (0);
+ graph_2=s_pop_b();
+ graph_3=s_get_b (0);
+
+ if (!check_index_flag && graph_2->instruction_code==GLOAD_I &&
+ LESS_UNSIGNED (graph_2->instruction_parameters[0].i,(MAX_INDIRECT_OFFSET-ARRAY_ELEMENTS_OFFSET)>>2))
+ {
+ int offset;
+
+ offset=ARRAY_ELEMENTS_OFFSET+(graph_2->instruction_parameters[0].i<<2);
+
+ graph_5=g_load_s_x (graph_1,offset,0,NULL);
+ graph_4=g_store_s_x (graph_3,graph_1,offset,0,NULL);
+ } else {
+ int offset;
+
+ if (check_index_flag)
+ graph_2=g_bounds (graph_1,graph_2);
+
+ graph_2=optimize_array_index (ARRAY_ELEMENTS_OFFSET,2,graph_2,&offset);
+ graph_5=g_load_s_x (graph_1,offset,2,graph_2);
+ graph_4=g_store_s_x (graph_3,graph_1,offset,2,graph_2);
+ }
+
+ s_put_b (0,graph_5);
+ s_put_a (0,graph_4);
+}
+#endif
static INSTRUCTION_GRAPH char_or_bool_array_offset (int offset,INSTRUCTION_GRAPH graph_1)
{
@@ -6252,7 +6331,7 @@ static void code_replaceR (VOID)
#if defined (M68000) || defined (I486)
int offset;
- graph_2=optimize_array_index (REAL_ARRAY_ELEMENTS_OFFSET,3,graph_2,&offset);
+ graph_2=optimize_array_index (ARRAY_ELEMENTS_OFFSET,3,graph_2,&offset);
graph_4=g_fload_x (graph_1,offset,3,graph_2);
graph_8=g_fstore_x (graph_7,graph_1,offset,3,graph_2);
#else
@@ -6286,6 +6365,43 @@ static void code_replaceR (VOID)
s_push_b (graph_9);
}
+#ifdef G_AI64
+static void code_replaceR32 (VOID)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4,graph_7,graph_8,graph_9;
+
+ graph_1=s_get_a (0);
+ graph_2=s_pop_b();
+ graph_3=s_pop_b();
+
+ if (check_index_flag)
+ graph_2=g_bounds (graph_1,graph_2);
+
+ graph_7=g_fp_arg (graph_3);
+
+ if (!check_index_flag && graph_2->instruction_code==GLOAD_I &&
+ LESS_UNSIGNED (graph_2->instruction_parameters[0].i,(MAX_INDIRECT_OFFSET-ARRAY_ELEMENTS_OFFSET)>>2))
+ {
+ int offset;
+
+ offset=ARRAY_ELEMENTS_OFFSET+(graph_2->instruction_parameters[0].i<<2);
+ graph_4=g_fload_s_x (graph_1,offset,0,NULL);
+ graph_8=g_fstore_s_x (graph_7,graph_1,offset,0,NULL);
+ } else {
+ int offset;
+
+ graph_2=optimize_array_index (ARRAY_ELEMENTS_OFFSET,2,graph_2,&offset);
+ graph_4=g_fload_s_x (graph_1,offset,2,graph_2);
+ graph_8=g_fstore_s_x (graph_7,graph_1,offset,2,graph_2);
+ }
+
+ graph_9=g_fromf (graph_4);
+
+ s_put_a (0,graph_8);
+ s_push_b (graph_9);
+}
+#endif
+
static void code_r_replace (int a_size,int b_size)
{
INSTRUCTION_GRAPH graph_1,graph_2,graph_3;
@@ -6403,9 +6519,17 @@ void code_replace (char element_descriptor[],int a_size,int b_size)
}
break;
case 'I':
- if (element_descriptor[1]=='N' && element_descriptor[2]=='T' && element_descriptor[3]=='\0'){
- code_replaceI();
- return;
+ if (element_descriptor[1]=='N' && element_descriptor[2]=='T'){
+ if (element_descriptor[3]=='\0'){
+ code_replaceI();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[3]=='3' && element_descriptor[4]=='2' && element_descriptor[5]=='\0'){
+ code_replaceI32();
+ return;
+ }
+#endif
}
break;
case 'P':
@@ -6415,11 +6539,17 @@ void code_replace (char element_descriptor[],int a_size,int b_size)
}
break;
case 'R':
- if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L' &&
- element_descriptor[4]=='\0')
- {
- code_replaceR();
- return;
+ if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L'){
+ if (element_descriptor[4]=='\0'){
+ code_replaceR();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[4]=='3' && element_descriptor[5]=='2' && element_descriptor[6]=='\0'){
+ code_replaceR32();
+ return;
+ }
+#endif
}
break;
case 'A':
@@ -6919,6 +7049,32 @@ static void code_selectI (VOID)
s_put_b (0,graph_3);
}
+#ifdef G_AI64
+static void code_selectI32 (VOID)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3;
+
+ graph_1=s_pop_a();
+ graph_2=s_get_b (0);
+
+ if (!check_index_flag && graph_2->instruction_code==GLOAD_I &&
+ LESS_UNSIGNED (graph_2->instruction_parameters[0].i,(MAX_INDIRECT_OFFSET-ARRAY_ELEMENTS_OFFSET)>>2))
+ {
+ graph_3=g_load_s_x (graph_1,ARRAY_ELEMENTS_OFFSET+(graph_2->instruction_parameters[0].i<<2),0,NULL);
+ } else {
+ int offset;
+
+ if (check_index_flag)
+ graph_2=g_bounds (graph_1,graph_2);
+
+ graph_2=optimize_array_index (ARRAY_ELEMENTS_OFFSET,2,graph_2,&offset);
+ graph_3=g_load_s_x (graph_1,offset,2,graph_2);
+ }
+
+ s_put_b (0,graph_3);
+}
+#endif
+
static void code_selectR (VOID)
{
INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4,graph_5,graph_6;
@@ -6991,6 +7147,34 @@ static void code_selectR (VOID)
s_push_b (graph_5);
}
+#ifdef G_AI64
+static void code_selectR32 (VOID)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4,graph_5,graph_6;
+
+ graph_1=s_pop_a();
+ graph_2=s_pop_b();
+
+ if (check_index_flag)
+ graph_2=g_bounds (graph_1,graph_2);
+
+ if (!check_index_flag && graph_2->instruction_code==GLOAD_I &&
+ LESS_UNSIGNED (graph_2->instruction_parameters[0].i,(MAX_INDIRECT_OFFSET-ARRAY_ELEMENTS_OFFSET)>>2))
+ {
+ graph_4=g_fload_s_x (graph_1,ARRAY_ELEMENTS_OFFSET+(graph_2->instruction_parameters[0].i<<2),0,NULL);
+ } else {
+ int offset;
+
+ graph_2=optimize_array_index (ARRAY_ELEMENTS_OFFSET,2,graph_2,&offset);
+ graph_4=g_fload_s_x (graph_1,offset,2,graph_2);
+ }
+
+ graph_5=g_fromf (graph_4);
+
+ s_push_b (graph_5);
+}
+#endif
+
static void code_r_select (int a_size,int b_size)
{
INSTRUCTION_GRAPH graph_1,graph_2,graph_3;
@@ -7065,9 +7249,17 @@ void code_select (char element_descriptor[],int a_size,int b_size)
}
break;
case 'I':
- if (element_descriptor[1]=='N' && element_descriptor[2]=='T' && element_descriptor[3]=='\0'){
- code_selectI();
- return;
+ if (element_descriptor[1]=='N' && element_descriptor[2]=='T'){
+ if (element_descriptor[3]=='\0'){
+ code_selectI();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[3]=='3' && element_descriptor[4]=='2' && element_descriptor[5]=='\0'){
+ code_selectI32();
+ return;
+ }
+#endif
}
break;
case 'P':
@@ -7077,11 +7269,17 @@ void code_select (char element_descriptor[],int a_size,int b_size)
}
break;
case 'R':
- if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L' &&
- element_descriptor[4]=='\0')
- {
- code_selectR();
- return;
+ if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L'){
+ if (element_descriptor[4]=='\0'){
+ code_selectR();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[4]=='3' && element_descriptor[5]=='2' && element_descriptor[6]=='\0'){
+ code_selectR32();
+ return;
+ }
+#endif
}
break;
case 'A':
@@ -7215,7 +7413,7 @@ void code_shiftl (VOID)
graph_2=remove_and_31_or_63 (graph_2);
#endif
graph_3=g_lsl (graph_2,graph_1);
-
+
s_put_b (0,graph_3);
}
@@ -7287,6 +7485,33 @@ void code_sinR (VOID)
#endif
}
+#if defined (I486) && !defined (G_AI64)
+void code_sincosR (VOID)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4,graph_5,graph_6,graph_7,graph_8,graph_9,graph_10;
+
+ graph_2=s_get_b (1);
+ graph_1=s_get_b (0);
+ graph_3=g_fjoin (graph_1,graph_2);
+
+ graph_4=g_instruction_1 (GFSINCOS,graph_3);
+
+ graph_5=g_instruction_2 (GFRESULT1,graph_4,NULL);
+ graph_6=g_instruction_2 (GFRESULT0,graph_4,NULL);
+ graph_5->instruction_parameters[1].p=graph_6;
+ graph_6->instruction_parameters[1].p=graph_5;
+
+ g_fhighlow (graph_7,graph_8,graph_5);
+ g_fhighlow (graph_9,graph_10,graph_6);
+
+ s_put_b (1,graph_8);
+ s_put_b (0,graph_7);
+
+ s_push_b (graph_10);
+ s_push_b (graph_9);
+}
+#endif
+
void code_sqrtR (VOID)
{
#ifdef M68000
@@ -7578,6 +7803,33 @@ static void code_updateI (VOID)
s_put_a (0,graph_4);
}
+#ifdef G_AI64
+static void code_updateI32 (VOID)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4;
+
+ graph_1=s_get_a (0);
+ graph_2=s_pop_b();
+ graph_3=s_pop_b();
+
+ if (!check_index_flag && graph_2->instruction_code==GLOAD_I &&
+ LESS_UNSIGNED (graph_2->instruction_parameters[0].i,(MAX_INDIRECT_OFFSET-ARRAY_ELEMENTS_OFFSET)>>2))
+ {
+ graph_4=g_store_x (graph_3,graph_1,ARRAY_ELEMENTS_OFFSET+(graph_2->instruction_parameters[0].i<<2),0,NULL);
+ } else {
+ int offset;
+
+ if (check_index_flag)
+ graph_2=g_bounds (graph_1,graph_2);
+
+ graph_2=optimize_array_index (ARRAY_ELEMENTS_OFFSET,2,graph_2,&offset);
+ graph_4=g_store_s_x (graph_3,graph_1,offset,2,graph_2);
+ }
+
+ s_put_a (0,graph_4);
+}
+#endif
+
static void code_updateR (VOID)
{
INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_4,graph_5,graph_6,graph_7,graph_8;
@@ -7649,6 +7901,35 @@ static void code_updateR (VOID)
s_put_a (0,graph_8);
}
+#ifdef G_AI64
+static void code_updateR32 (VOID)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3,graph_7,graph_8;
+
+ graph_1=s_get_a (0);
+ graph_2=s_pop_b();
+ graph_3=s_pop_b();
+
+ if (check_index_flag)
+ graph_2=g_bounds (graph_1,graph_2);
+
+ graph_7=g_fp_arg (graph_3);
+
+ if (!check_index_flag && graph_2->instruction_code==GLOAD_I &&
+ LESS_UNSIGNED (graph_2->instruction_parameters[0].i,(MAX_INDIRECT_OFFSET-REAL_ARRAY_ELEMENTS_OFFSET)>>2))
+ {
+ graph_8=g_fstore_s_x (graph_7,graph_1,REAL_ARRAY_ELEMENTS_OFFSET+(graph_2->instruction_parameters[0].i<<2),0,NULL);
+ } else {
+ int offset;
+
+ graph_2=optimize_array_index (REAL_ARRAY_ELEMENTS_OFFSET,2,graph_2,&offset);
+ graph_8=g_fstore_s_x (graph_7,graph_1,offset,2,graph_2);
+ }
+
+ s_put_a (0,graph_8);
+}
+#endif
+
static int equal_graph (INSTRUCTION_GRAPH graph_0,INSTRUCTION_GRAPH graph_1)
{
if (graph_0==graph_1)
@@ -7809,9 +8090,17 @@ void code_update (char element_descriptor[],int a_size,int b_size)
}
break;
case 'I':
- if (element_descriptor[1]=='N' && element_descriptor[2]=='T' && element_descriptor[3]=='\0'){
- code_updateI();
- return;
+ if (element_descriptor[1]=='N' && element_descriptor[2]=='T'){
+ if (element_descriptor[3]=='\0'){
+ code_updateI();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[3]=='3' && element_descriptor[4]=='2' && element_descriptor[5]=='\0'){
+ code_updateI32();
+ return;
+ }
+#endif
}
break;
case 'P':
@@ -7821,11 +8110,17 @@ void code_update (char element_descriptor[],int a_size,int b_size)
}
break;
case 'R':
- if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L' &&
- element_descriptor[4]=='\0')
- {
- code_updateR();
- return;
+ if (element_descriptor[1]=='E' && element_descriptor[2]=='A' && element_descriptor[3]=='L'){
+ if (element_descriptor[4]=='\0'){
+ code_updateR();
+ return;
+ }
+#ifdef G_AI64
+ if (element_descriptor[4]=='3' && element_descriptor[5]=='2' && element_descriptor[6]=='\0'){
+ code_updateR32();
+ return;
+ }
+#endif
}
break;
case 'A':
@@ -9336,6 +9631,10 @@ void initialize_coding (VOID)
create_arrayB__label=create_arrayC__label=create_arrayI__label=create_arrayR__label=create_r_array__label=NULL;
push_a_r_args_label=index_error_label=NULL;
+#ifdef G_AI64
+ create_arrayI32_label=create_arrayR32_label=NULL;
+#endif
+
small_integers_label=static_characters_label=NULL;
eval_fill_label=NULL;
diff --git a/cgcodep.h b/cgcodep.h
index d716abe..2ee9a72 100644
--- a/cgcodep.h
+++ b/cgcodep.h
@@ -253,6 +253,9 @@ void code_shiftl (VOID);
void code_shiftr (VOID);
void code_shiftrU (VOID);
void code_sinR (VOID);
+#if defined (I486) && !defined (G_AI64)
+void code_sincosR (VOID);
+#endif
void code_sliceS (int source_offset,int destination_offset);
void code_sqrtR (VOID);
void code_stop_reducer (VOID);
diff --git a/cgconst.h b/cgconst.h
index f7699a1..71ebdf0 100644
--- a/cgconst.h
+++ b/cgconst.h
@@ -18,7 +18,7 @@ enum {
,GNOT
#endif
#ifndef G_A64
- ,GFHIGH,GFJOIN,GFLOW
+ ,GFHIGH,GFJOIN,GFLOW,
#else
,GFROMF,GTOF
#endif
@@ -31,6 +31,12 @@ enum {
#ifdef I486
,GADDDU, GDIVDU, GMULUD, GREMU, GRESULT0, GRESULT1, GSUBDU
#endif
+#if defined (I486) && !defined (G_A64)
+ ,GFSINCOS, GFRESULT0, GFRESULT1
+#endif
+#ifdef G_AI64
+ ,GLOAD_S_X, GSTORE_S_X, GFLOAD_S_X, GFSTORE_S_X
+#endif
#ifdef M68000
,GFACOS, GFASIN, GFEXP, GFLN, GFLOG10
#endif
diff --git a/cgias.c b/cgias.c
index 38d6c83..8803735 100644
--- a/cgias.c
+++ b/cgias.c
@@ -880,7 +880,7 @@ static void as_x_r (int code,int offset,struct index_registers *index_registers,
if (reg2==ESP)
internal_error_in_function ("as_x_r");
-
+
store_c (code);
if (offset==0 && reg1!=EBP){
store_c (0x04 | (reg_num (reg3)<<3));
@@ -2637,6 +2637,43 @@ static void as_mulud_instruction (struct instruction *instruction)
reg_1=instruction->instruction_parameters[0].parameter_data.reg.r;
reg_2=instruction->instruction_parameters[1].parameter_data.reg.r;
+#if 0
+ reg_3=instruction->instruction_parameters[2].parameter_data.reg.r;
+
+ if (reg_3==REGISTER_D0){
+ if (reg_1==REGISTER_A1){
+ as_move_r_r (reg_2,REGISTER_D0);
+ as_r (0367,040,reg_1); /* mul */
+ as_move_r_r (REGISTER_D0,reg_2);
+ } else if (reg_2==REGISTER_A1){
+ as_move_r_r (reg_2,REGISTER_D0);
+ as_r (0367,040,reg_1); /* mul */
+ as_2move_registers (REGISTER_D0,REGISTER_A1,reg_1);
+ } else {
+ as_2move_registers (REGISTER_A1,reg_2,REGISTER_D0);
+ as_r (0367,040,reg_1); /* mul */
+ as_3move_registers (REGISTER_D0,reg_2,REGISTER_A1,reg_1);
+ }
+ return;
+ }
+
+ if (reg_3==REGISTER_A1){
+ if (reg_2==REGISTER_D0){
+ as_r (0367,040,reg_1); /* mul */
+ as_move_r_r (REGISTER_A1,reg_1);
+ } else if (reg_1==REGISTER_D0){
+ as_r (0367,040,reg_2); /* mul */
+ as_2move_registers (REGISTER_A1,REGISTER_D0,reg_2);
+ } else {
+ store_c (0x90+reg_num (reg_2)); /* xchg reg_2,D0 */
+ as_r (0367,040,reg_1); /* mul */
+ store_c (0x90+reg_num (reg_2)); /* xchg reg_2,D0 */
+ as_move_r_r (REGISTER_A1,reg_1);
+ }
+ return;
+ }
+#endif
+
if (reg_2==REGISTER_D0){
if (reg_1==REGISTER_A1)
as_r (0367,040,reg_1); /* mul */
@@ -3028,7 +3065,7 @@ struct instruction *find_next_fp_instruction (struct instruction *instruction)
#endif
case IFSEQ: case IFSGE: case IFSGT: case IFSLE: case IFSLT: case IFSNE:
case IFCEQ: case IFCGE: case IFCGT: case IFCLE: case IFCLT: case IFCNE:
- case IFCOS: case IFSIN: case IFSQRT: case IFTAN:
+ case IFCOS: case IFSIN: case IFSQRT: case IFTAN: case IFSINCOS:
case IFEXG:
case IWORD:
return instruction;
@@ -3727,6 +3764,44 @@ static void as_monadic_float_instruction (struct instruction *instruction,int co
#endif
}
+static void as_fsincos_instruction (struct instruction *instruction)
+{
+ int f_reg1,f_reg2;
+
+ f_reg1=instruction->instruction_parameters[0].parameter_data.reg.r;
+ f_reg2=instruction->instruction_parameters[1].parameter_data.reg.r;
+
+ if (f_reg1!=0){
+ store_c (0xd9); /* fxch f1 */
+ store_c (0xc8+f_reg1);
+ }
+
+ store_c (0xd9); /* fsincos */
+ store_c (0xfb);
+
+ if (f_reg1==0){
+#ifdef FP_STACK_OPTIMIZATIONS
+ fstpl_instruction (f_reg2,instruction);
+#else
+ as_f_r (0xdd,0xd8,f_reg2+1); /* fstp */
+#endif
+ } else if (f_reg2==0){
+ store_c (0xd9); /* fxch st(1) */
+ store_c (0xc8+1);
+
+#ifdef FP_STACK_OPTIMIZATIONS
+ fstpl_instruction (f_reg1,instruction);
+#else
+ as_f_r (0xdd,0xd8,f_reg1+1); /* fstp */
+#endif
+ } else {
+ as_f_r (0xdd,0xd8,f_reg2+1); /* fstp */
+
+ store_c (0xd9); /* fxch f1 */
+ store_c (0xc8+f_reg1);
+ }
+}
+
static void as_test_floating_point_condition_code (int n)
{
store_c (0xdf);
@@ -4245,7 +4320,7 @@ static void as_instructions (struct instruction *instruction)
case IBTST:
as_btst_instruction (instruction);
break;
- case IMOVEW:
+ case IMOVEDB:
as_movew_instruction (instruction);
break;
case IMOVEB:
@@ -4384,7 +4459,10 @@ static void as_instructions (struct instruction *instruction)
case IFEXG:
as_fexg (instruction);
break;
-#endif
+#endif
+ case IFSINCOS:
+ as_fsincos_instruction (instruction);
+ break;
default:
internal_error_in_function ("as_instructions");
}
diff --git a/cgiconst.h b/cgiconst.h
index fe4d373..7b93eb4 100644
--- a/cgiconst.h
+++ b/cgiconst.h
@@ -20,7 +20,7 @@ enum {
IFCMP, IFCOS, IFDIV, IFMUL, IFNEG, IFREM, IFSEQ,
IFSGE, IFSGT, IFSIN, IFSLE, IFSLT, IFSNE, IFSUB,
IFTAN, IFTST, IFMOVE, IFMOVEL, IJMP, IJSR, ILEA,
- ILSL, ILSR, IMOD, IMOVE, IMOVEB, IMOVEW, IMUL,
+ ILSL, ILSR, IMOD, IMOVE, IMOVEB, IMOVEDB, IMUL,
INEG, IOR, IRTS, ISCHEDULE, ISEQ, ISGE, ISGEU,
ISGT, ISGTU, ISLE, ISLEU, ISLT, ISLTU, ISNE,
ISNO, ISO, ISUB, ITST, IWORD
@@ -53,6 +53,7 @@ enum {
#endif
#if defined (I486) && !defined (G_A64)
,IFCEQ, IFCGE, IFCGT, IFCLE, IFCLT, IFCNE
+ ,IFSINCOS
#endif
#ifdef G_POWER
,ICMPLW
@@ -74,7 +75,7 @@ enum {
,IUMULH
#endif
#ifdef G_AI64
- ,IMOVESW
+ ,ILOADSQB, IMOVEQB, IFLOADS, IFCVT2S, IFMOVES
#endif
};
diff --git a/cginput.c b/cginput.c
index ad82bc2..21be774 100644
--- a/cginput.c
+++ b/cginput.c
@@ -2095,6 +2095,9 @@ static void put_instructions_in_table2 (void)
put_instruction_name ("shiftr%", parse_instruction, code_shiftr );
put_instruction_name ("shiftrU", parse_instruction, code_shiftrU );
put_instruction_name ("sinR", parse_instruction, code_sinR );
+#if defined (I486) && !defined (G_AI64)
+ put_instruction_name ("sincosR", parse_instruction, code_sincosR );
+#endif
put_instruction_name ("sliceS", parse_instruction_n_n, code_sliceS );
put_instruction_name ("sqrtR", parse_instruction, code_sqrtR );
put_instruction_name ("stop_reducer", parse_instruction, code_stop_reducer );
diff --git a/cginstructions.c b/cginstructions.c
index b2c2b20..25c11a8 100644
--- a/cginstructions.c
+++ b/cginstructions.c
@@ -87,8 +87,6 @@ LABEL *realloc_0_label,*realloc_1_label,*realloc_2_label,*realloc_3_label,
LABEL *end_a_stack_label,*end_b_stack_label;
#endif
-#pragma segment Code20
-
INSTRUCTION_GRAPH g_new_node (int instruction_code,int arity,int arg_size)
{
INSTRUCTION_GRAPH instruction;
@@ -675,6 +673,26 @@ INSTRUCTION_GRAPH g_fload_x (INSTRUCTION_GRAPH graph_1,int offset,int shift,INST
return instruction;
}
+#ifdef G_AI64
+INSTRUCTION_GRAPH g_fload_s_x (INSTRUCTION_GRAPH graph_1,int offset,int shift,INSTRUCTION_GRAPH graph_2)
+{
+ INSTRUCTION_GRAPH instruction;
+
+ instruction=g_new_node (GFLOAD_S_X,0,4*sizeof (union instruction_parameter));
+
+ instruction->instruction_parameters[0].p=graph_1;
+ instruction->instruction_parameters[1].i=(offset<<2) | shift;
+ instruction->instruction_parameters[2].p=graph_2;
+ instruction->instruction_parameters[3].p=load_indexed_list;
+
+ graph_1->instruction_d_min_a_cost+=1;
+
+ load_indexed_list=instruction;
+
+ return instruction;
+}
+#endif
+
INSTRUCTION_GRAPH g_fstore (int offset,int reg_1,INSTRUCTION_GRAPH graph_1,
#ifdef G_A64
INSTRUCTION_GRAPH graph_2)
@@ -869,6 +887,26 @@ INSTRUCTION_GRAPH g_load_des_id (int offset,INSTRUCTION_GRAPH graph_1)
return instruction;
}
+#ifdef G_AI64
+INSTRUCTION_GRAPH g_load_s_x (INSTRUCTION_GRAPH graph_1,int offset,int shift,INSTRUCTION_GRAPH graph_2)
+{
+ INSTRUCTION_GRAPH instruction;
+
+ instruction=g_new_node (GLOAD_S_X,0,4*sizeof (union instruction_parameter));
+
+ instruction->instruction_parameters[0].p=graph_1;
+ instruction->instruction_parameters[1].imm=(((CleanInt)offset)<<4) | (shift<<2);
+ instruction->instruction_parameters[2].p=graph_2;
+ instruction->instruction_parameters[3].p=load_indexed_list;
+
+ graph_1->instruction_d_min_a_cost+=1;
+
+ load_indexed_list=instruction;
+
+ return instruction;
+}
+#endif
+
INSTRUCTION_GRAPH g_movem (int offset,INSTRUCTION_GRAPH graph_1,int n)
{
INSTRUCTION_GRAPH instruction;
@@ -915,7 +953,7 @@ INSTRUCTION_GRAPH g_fregister (int float_reg)
INSTRUCTION_GRAPH g_fstore_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3)
{
- register INSTRUCTION_GRAPH instruction;
+ INSTRUCTION_GRAPH instruction;
instruction=g_new_node (GFSTORE_X,0,5*sizeof (union instruction_parameter));
@@ -935,6 +973,25 @@ INSTRUCTION_GRAPH g_fstore_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_
return instruction;
}
+#ifdef G_AI64
+INSTRUCTION_GRAPH g_fstore_s_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3)
+{
+ INSTRUCTION_GRAPH instruction;
+
+ instruction=g_new_node (GFSTORE_S_X,0,5*sizeof (union instruction_parameter));
+
+ instruction->instruction_parameters[0].p=graph_1;
+ instruction->instruction_parameters[1].p=graph_2;
+ instruction->instruction_parameters[2].i=(offset<<2) | shift;
+ instruction->instruction_parameters[3].p=graph_3;
+ instruction->instruction_parameters[4].p=load_indexed_list;
+
+ graph_2->instruction_d_min_a_cost+=1;
+
+ return instruction;
+}
+#endif
+
INSTRUCTION_GRAPH g_g_register (int reg)
{
INSTRUCTION_GRAPH instruction;
@@ -1003,6 +1060,25 @@ INSTRUCTION_GRAPH g_store_b_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph
return instruction;
}
+#ifdef G_AI64
+INSTRUCTION_GRAPH g_store_s_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3)
+{
+ INSTRUCTION_GRAPH instruction;
+
+ instruction=g_new_node (GSTORE_S_X,0,5*sizeof (union instruction_parameter));
+
+ instruction->instruction_parameters[0].p=graph_1;
+ instruction->instruction_parameters[1].p=graph_2;
+ instruction->instruction_parameters[2].imm=(((CleanInt)offset)<<4) | (shift<<2);
+ instruction->instruction_parameters[3].p=graph_3;
+ instruction->instruction_parameters[4].p=load_indexed_list;
+
+ graph_2->instruction_d_min_a_cost+=1;
+
+ return instruction;
+}
+#endif
+
INSTRUCTION_GRAPH g_store_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3)
{
INSTRUCTION_GRAPH instruction;
@@ -3912,7 +3988,7 @@ void code_ccall (char *c_function_name,char *s,int length)
for (l=first_pointer_result_index; l<length; ++l){
switch (s[l]){
case 'I':
- i_movesw_id_r (b_o,B_STACK_POINTER,REGISTER_RBP);
+ i_loadsqb_id_r (b_o,B_STACK_POINTER,REGISTER_RBP);
i_move_r_id (REGISTER_RBP,b_o,B_STACK_POINTER);
b_o+=STACK_ELEMENT_SIZE;
break;
@@ -3932,7 +4008,7 @@ void code_ccall (char *c_function_name,char *s,int length)
switch (result){
case 'I':
- i_movesw_r_r (REGISTER_D0,REGISTER_D0);
+ i_loadsqb_r_r (REGISTER_D0,REGISTER_D0);
case 'p':
begin_new_basic_block();
init_b_stack (1,i_vector);
diff --git a/cginstructions.h b/cginstructions.h
index b86f12f..d587abe 100644
--- a/cginstructions.h
+++ b/cginstructions.h
@@ -22,6 +22,9 @@ extern INSTRUCTION_GRAPH g_fload (int offset,int stack);
extern INSTRUCTION_GRAPH g_fload_i (DOUBLE v);
extern INSTRUCTION_GRAPH g_fload_id (int offset,INSTRUCTION_GRAPH graph_1);
extern INSTRUCTION_GRAPH g_fload_x (INSTRUCTION_GRAPH graph_1,int offset,int shift,INSTRUCTION_GRAPH graph_2);
+#ifdef G_AI64
+extern INSTRUCTION_GRAPH g_fload_s_x (INSTRUCTION_GRAPH graph_1,int offset,int shift,INSTRUCTION_GRAPH graph_2);
+#endif
extern INSTRUCTION_GRAPH g_lea (LABEL *label);
extern INSTRUCTION_GRAPH g_lea_i (LABEL *label,int offset);
extern INSTRUCTION_GRAPH g_load (int offset,int stack);
@@ -32,14 +35,23 @@ extern INSTRUCTION_GRAPH g_load_x (INSTRUCTION_GRAPH graph_1,int offset,int shif
extern INSTRUCTION_GRAPH g_load_b_id (int offset,INSTRUCTION_GRAPH graph_1);
extern INSTRUCTION_GRAPH g_load_des_i (LABEL *descriptor_label,int arity);
extern INSTRUCTION_GRAPH g_load_des_id (int offset,INSTRUCTION_GRAPH graph_1);
+#ifdef G_AI64
+extern INSTRUCTION_GRAPH g_load_s_x (INSTRUCTION_GRAPH graph_1,int offset,int shift,INSTRUCTION_GRAPH graph_2);
+#endif
extern INSTRUCTION_GRAPH g_movem (int offset,INSTRUCTION_GRAPH graph_1,int n);
extern INSTRUCTION_GRAPH g_movemi (int number,INSTRUCTION_GRAPH movem_graph);
extern INSTRUCTION_GRAPH g_fregister (int float_reg);
extern INSTRUCTION_GRAPH g_fstore_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3);
+#ifdef G_AI64
+extern INSTRUCTION_GRAPH g_fstore_s_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3);
+#endif
extern INSTRUCTION_GRAPH g_g_register (int reg);
extern INSTRUCTION_GRAPH g_register (int reg);
extern INSTRUCTION_GRAPH g_store (int offset,int reg_1,INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2);
extern INSTRUCTION_GRAPH g_store_b_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,INSTRUCTION_GRAPH graph_3);
+#ifdef G_AI64
+extern INSTRUCTION_GRAPH g_store_s_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3);
+#endif
extern INSTRUCTION_GRAPH g_store_x (INSTRUCTION_GRAPH graph_1,INSTRUCTION_GRAPH graph_2,int offset,int shift,INSTRUCTION_GRAPH graph_3);
extern INSTRUCTION_GRAPH g_store_r (int reg_1,INSTRUCTION_GRAPH graph_1);
diff --git a/cgiwas.c b/cgiwas.c
index d59dc6e..2fa7cfd 100644
--- a/cgiwas.c
+++ b/cgiwas.c
@@ -2843,6 +2843,47 @@ static void w_as_monadic_float_instruction (struct instruction *instruction,char
#endif
}
+static void w_as_fsincos_instruction (struct instruction *instruction)
+{
+ int f_reg1,f_reg2;
+
+ f_reg1=instruction->instruction_parameters[0].parameter_data.reg.r;
+ f_reg2=instruction->instruction_parameters[1].parameter_data.reg.r;
+
+ if (f_reg1!=0){
+ w_as_opcode ("fxch");
+ w_as_fp_register_newline (f_reg1);
+ }
+
+ w_as_opcode ("fsincos");
+ w_as_newline();
+
+ if (f_reg1==0){
+#ifdef FP_STACK_OPTIMIZATIONS
+ fstpl_instruction (f_reg2,instruction);
+#else
+ w_as_opcode ("fstp");
+ w_as_fp_register_newline (f_reg2+1);
+#endif
+ } else if (f_reg2==0){
+ w_as_opcode ("fxch");
+ w_as_fp_register_newline (1);
+
+#ifdef FP_STACK_OPTIMIZATIONS
+ fstpl_instruction (f_reg1,instruction);
+#else
+ w_as_opcode ("fstp");
+ w_as_fp_register_newline (f_reg1+1);
+#endif
+ } else {
+ w_as_opcode ("fstp");
+ w_as_fp_register_newline (f_reg2+1);
+
+ w_as_opcode ("fxch");
+ w_as_fp_register_newline (f_reg1);
+ }
+}
+
static struct instruction *w_as_fmove_instruction (struct instruction *instruction)
{
switch (instruction->instruction_parameters[1].parameter_type){
@@ -3376,7 +3417,7 @@ static void w_as_instructions (register struct instruction *instruction)
case IBTST:
w_as_btst_instruction (instruction);
break;
- case IMOVEW:
+ case IMOVEDB:
w_as_move_instruction (instruction,SIZE_WORD);
break;
case IMOVEB:
@@ -3505,17 +3546,20 @@ static void w_as_instructions (register struct instruction *instruction)
case IFCNE:
w_as_convert_float_condition_instruction (instruction,3);
break;
-#ifdef FP_STACK_OPTIMIZATIONS
- case IFEXG:
- w_as_fexg (instruction);
- break;
-#endif
case IWORD:
w_as_word_instruction (instruction);
break;
case IRTSI:
w_as_rtsi_instruction (instruction);
break;
+#ifdef FP_STACK_OPTIMIZATIONS
+ case IFEXG:
+ w_as_fexg (instruction);
+ break;
+#endif
+ case IFSINCOS:
+ w_as_fsincos_instruction (instruction);
+ break;
case IFTST:
default:
internal_error_in_function ("w_as_instructions");
diff --git a/cglin.c b/cglin.c
index 2b21613..9be0f99 100644
--- a/cglin.c
+++ b/cglin.c
@@ -48,8 +48,6 @@ extern LABEL *index_error_label;
int local_data_offset;
-#pragma segment Code3
-
#define S2(s,v1,v2) s.v1;s.v2
#define S3(s,v1,v2,v3) s.v1;s.v2;s.v3
#define S4(s,v1,v2,v3,v4) s.v1;s.v2;s.v3;s.v4
@@ -409,6 +407,18 @@ void i_ext_r (int register_1)
}
#endif
+#ifdef G_AI64
+void i_fcvt2s_fr_fr (int register_1,int register_2)
+{
+ struct instruction *instruction;
+
+ instruction=i_new_instruction2 (IFCVT2S);
+
+ set_float_register_parameter (instruction->instruction_parameters[0],register_1);
+ set_float_register_parameter (instruction->instruction_parameters[1],register_2);
+}
+#endif
+
#ifdef FP_STACK_OPTIMIZATIONS
static void i_fexg_fr_fr (int register_1,int register_2)
{
@@ -421,6 +431,21 @@ static void i_fexg_fr_fr (int register_1,int register_2)
}
#endif
+#ifdef G_AI64
+static void i_floads_id_fr (int offset,int register_2,int register_1)
+{
+ struct instruction *instruction;
+
+ instruction=i_new_instruction2 (IFLOADS);
+
+ instruction->instruction_parameters[0].parameter_type=P_INDIRECT;
+ instruction->instruction_parameters[0].parameter_offset=offset;
+ instruction->instruction_parameters[0].parameter_data.i=register_2;
+
+ set_float_register_parameter (instruction->instruction_parameters[1],register_1);
+}
+#endif
+
void i_fmove_fr_fr (int register_1,int register_2)
{
struct instruction *instruction;
@@ -597,6 +622,49 @@ static void i_fmovel_fr_r (int register_1,int register_2)
parameter_data.i=register_2);
}
+#ifdef G_AI64
+static void i_fmoves_fr_id (int register_1,int offset,int register_2)
+{
+ struct instruction *instruction;
+
+ instruction=i_new_instruction2 (IFMOVES);
+
+ set_float_register_parameter (instruction->instruction_parameters[0],register_1);
+
+ instruction->instruction_parameters[1].parameter_type=P_INDIRECT;
+ instruction->instruction_parameters[1].parameter_offset=offset;
+ instruction->instruction_parameters[1].parameter_data.i=register_2;
+}
+
+static void i_fmoves_fr_x (int register_1,int offset,int register_2,int register_3)
+{
+ struct instruction *instruction;
+ struct index_registers *index_registers;
+
+ instruction=i_new_instruction (IFMOVES,2,2*sizeof (struct parameter)+sizeof (struct index_registers));
+ index_registers=(struct index_registers *)&instruction->instruction_parameters[2];
+
+ set_float_register_parameter (instruction->instruction_parameters[0],register_1);
+
+ S3(instruction->instruction_parameters[1],parameter_type=P_INDEXED,parameter_offset=offset,parameter_data.ir=index_registers);
+
+ index_registers->a_reg.r=register_2;
+ index_registers->d_reg.r=register_3;
+}
+#endif
+
+#if defined (I486) && !defined (G_AI64)
+static void i_fsincos_fr_fr (int register_1,int register_2)
+{
+ struct instruction *instruction;
+
+ instruction=i_new_instruction2 (IFSINCOS);
+
+ set_float_register_parameter (instruction->instruction_parameters[0],register_1);
+ set_float_register_parameter (instruction->instruction_parameters[1],register_2);
+}
+#endif
+
#ifdef ALIGN_REAL_ARRAYS
static void i_fmove_x_fr (int offset,int register_1,int register_2,int register_3,int flags)
#else
@@ -621,6 +689,26 @@ static void i_fmove_x_fr (int offset,int register_1,int register_2,int register_
set_float_register_parameter (instruction->instruction_parameters[1],register_3);
}
+#ifdef G_AI64
+static void i_floads_x_fr (int offset,int register_1,int register_2,int register_3)
+{
+ struct instruction *instruction;
+ struct index_registers *index_registers;
+
+ instruction=i_new_instruction (IFLOADS,2,2*sizeof (struct parameter)+sizeof (struct index_registers));
+ index_registers=(struct index_registers *)&instruction->instruction_parameters[2];
+
+ instruction->instruction_parameters[0].parameter_type=P_INDEXED;
+ instruction->instruction_parameters[0].parameter_offset=offset;
+ instruction->instruction_parameters[0].parameter_data.ir=index_registers;
+
+ index_registers->a_reg.r=register_1;
+ index_registers->d_reg.r=register_2;
+
+ set_float_register_parameter (instruction->instruction_parameters[1],register_3);
+}
+#endif
+
void i_jmp_id (int offset_1,int register_1,int n_a_registers)
{
struct instruction *instruction;
@@ -1053,11 +1141,11 @@ void i_movem_id_r (int offset,int register_1,int register_2)
#endif
#ifdef G_AI64
-void i_movesw_r_r (int register_1,int register_2)
+void i_loadsqb_r_r (int register_1,int register_2)
{
struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVESW);
+ instruction=i_new_instruction2 (ILOADSQB);
S2 (instruction->instruction_parameters[0], parameter_type=P_REGISTER,
parameter_data.i=register_1);
@@ -1066,11 +1154,11 @@ void i_movesw_r_r (int register_1,int register_2)
parameter_data.i=register_2);
}
-void i_movesw_id_r (int offset,int register_1,int register_2)
+void i_loadsqb_id_r (int offset,int register_1,int register_2)
{
struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVESW);
+ instruction=i_new_instruction2 (ILOADSQB);
S3 (instruction->instruction_parameters[0], parameter_type=P_INDIRECT,
parameter_offset=offset,
@@ -1079,13 +1167,33 @@ void i_movesw_id_r (int offset,int register_1,int register_2)
S2 (instruction->instruction_parameters[1], parameter_type=P_REGISTER,
parameter_data.i=register_2);
}
+
+static void i_loadsqb_x_r (CleanInt offset,int register_1,int register_2,int register_3)
+{
+ struct instruction *instruction;
+ struct index_registers *index_registers;
+
+ instruction=i_new_instruction
+ (ILOADSQB,2,2*sizeof (struct parameter)+sizeof (struct index_registers));
+ index_registers=(struct index_registers *)&instruction->instruction_parameters[2];
+
+ instruction->instruction_parameters[0].parameter_type=P_INDEXED;
+ instruction->instruction_parameters[0].parameter_offset=(offset>>2);
+ instruction->instruction_parameters[0].parameter_data.ir=index_registers;
+
+ index_registers->a_reg.r=register_1;
+ index_registers->d_reg.r=register_2;
+
+ instruction->instruction_parameters[1].parameter_type=P_REGISTER;
+ instruction->instruction_parameters[1].parameter_data.i=register_3;
+}
#endif
void i_movew_id_r (int offset,int register_1,int register_2)
{
register struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVEW);
+ instruction=i_new_instruction2 (IMOVEDB);
instruction->instruction_parameters[0].parameter_type=P_INDIRECT;
instruction->instruction_parameters[0].parameter_offset=offset;
@@ -1288,7 +1396,7 @@ void i_move_id_r (int offset,int register_1,int register_2)
{
struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVEW);
+ instruction=i_new_instruction2 (IMOVEDB);
instruction->instruction_parameters[0].parameter_type=P_INDIRECT;
instruction->instruction_parameters[0].parameter_offset=offset1;
@@ -1303,7 +1411,7 @@ void i_move_id_r (int offset,int register_1,int register_2)
{
struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVEW);
+ instruction=i_new_instruction2 (IMOVEDB);
instruction->instruction_parameters[0].parameter_type=P_REGISTER;
instruction->instruction_parameters[0].parameter_data.i=register_1;
@@ -1518,8 +1626,8 @@ void i_move_r_r (int register_1,int register_2)
static void i_move_x_r (int offset,int register_1,int register_2,int register_3)
{
- register struct instruction *instruction;
- register struct index_registers *index_registers;
+ struct instruction *instruction;
+ struct index_registers *index_registers;
instruction=i_new_instruction
(IMOVE,2,2*sizeof (struct parameter)+sizeof (struct index_registers));
@@ -1607,7 +1715,7 @@ void i_movew_id_pd (int offset_1,int register_1,int register_2)
{
register struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVEW);
+ instruction=i_new_instruction2 (IMOVEDB);
instruction->instruction_parameters[0].parameter_type=P_INDIRECT;
instruction->instruction_parameters[0].parameter_offset=offset_1;
@@ -1621,7 +1729,7 @@ void i_movew_pi_id (int register_1,int offset_2,int register_2)
{
struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVEW);
+ instruction=i_new_instruction2 (IMOVEDB);
instruction->instruction_parameters[0].parameter_type=P_POST_INCREMENT;
instruction->instruction_parameters[0].parameter_data.i=register_1;
@@ -1635,7 +1743,7 @@ void i_movew_pi_r (int register_1,int register_2)
{
struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVEW);
+ instruction=i_new_instruction2 (IMOVEDB);
instruction->instruction_parameters[0].parameter_type=P_POST_INCREMENT;
instruction->instruction_parameters[0].parameter_data.i=register_1;
@@ -1648,7 +1756,7 @@ void i_movew_r_pd (int register_1,int register_2)
{
struct instruction *instruction;
- instruction=i_new_instruction2 (IMOVEW);
+ instruction=i_new_instruction2 (IMOVEDB);
S2 (instruction->instruction_parameters[0], parameter_type=P_REGISTER,
parameter_data.i=register_1);
@@ -3039,7 +3147,7 @@ static void float_register_node (register INSTRUCTION_GRAPH graph,int reg)
{
graph->instruction_code=GFREGISTER;
graph->instruction_parameters[0].i=reg;
-
+
if ((unsigned)reg<(unsigned)N_FLOAT_PARAMETER_REGISTERS)
global_block.block_graph_f_register_parameter_node [reg]=graph;
}
@@ -6425,7 +6533,7 @@ static void linearize_fjoin_operator (INSTRUCTION_GRAPH graph,register ADDRESS *
static int float_compare_node (INSTRUCTION_GRAPH graph,int i_test_1,int i_test_2)
{
ADDRESS ad_1,ad_2;
-
+
linearize_float_graph (graph->instruction_parameters[0].p,&ad_1);
linearize_float_graph (graph->instruction_parameters[1].p,&ad_2);
@@ -6774,6 +6882,111 @@ static void linearize_fload_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
}
}
+#ifdef G_AI64
+static void linearize_fload_s_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2;
+ int offset,reg_1;
+
+ graph_1=graph->instruction_parameters[0].p;
+ offset=graph->instruction_parameters[1].i;
+ graph_2=graph->instruction_parameters[2].p;
+
+ if (graph_2!=NULL){
+ ADDRESS ad_1;
+
+ if (graph->order_left){
+ linearize_graph (graph_1,ad_p);
+ linearize_graph (graph_2,&ad_1);
+ } else {
+ linearize_graph (graph_2,&ad_1);
+ linearize_graph (graph_1,ad_p);
+ }
+
+ in_data_register (&ad_1);
+ in_address_register (ad_p);
+
+ if (--*ad_p->ad_count_p==0)
+ free_aregister (ad_p->ad_register);
+ if (--*ad_1.ad_count_p==0)
+ free_dregister (ad_1.ad_register);
+
+ reg_1=get_fregister();
+
+ i_floads_x_fr (offset,ad_p->ad_register,ad_1.ad_register,reg_1);
+ } else {
+ linearize_graph (graph_1,ad_p);
+ in_address_register (ad_p);
+
+ if (--*ad_p->ad_count_p==0)
+ free_aregister (ad_p->ad_register);
+
+ reg_1=get_fregister();
+
+ i_floads_id_fr (offset>>2,ad_p->ad_register,reg_1);
+ }
+
+ ad_p->ad_mode=P_F_REGISTER;
+ ad_p->ad_register=reg_1;
+ ad_p->ad_count_p=&graph->node_count;
+
+ if (graph->node_count<=1)
+ graph->inode_arity=(graph->inode_arity & ~LOAD_X_TO_ADDRESS) | LOAD_X_TO_REGISTER;
+ else
+ float_register_node (graph,reg_1);
+}
+#endif
+
+#if defined (I486) && !defined (G_AI64)
+static void linearize_two_float_results_operator (INSTRUCTION_GRAPH result_graph,ADDRESS *ad_p)
+{
+ INSTRUCTION_GRAPH graph,result_graph2;
+ ADDRESS ad_1;
+ int reg_1,reg_2;
+
+ graph=result_graph->instruction_parameters[0].p;
+
+ if (graph->instruction_code==GFSINCOS){
+ INSTRUCTION_GRAPH graph_1,graph_2;
+
+ graph_1=graph->instruction_parameters[0].p;
+ linearize_float_graph (graph_1,&ad_1);
+ in_alterable_float_register (&ad_1);
+
+ reg_1=ad_1.ad_register;
+ reg_2=get_fregister();
+
+ i_fsincos_fr_fr (reg_1,reg_2);
+ } else
+ internal_error_in_function ("linearize_two_float_results_operator");
+
+ result_graph2=result_graph->instruction_parameters[1].p;
+
+ ad_p->ad_mode=P_F_REGISTER;
+ ad_p->ad_count_p=&result_graph->node_count;
+
+ if (result_graph->instruction_code==GFRESULT0){
+ ad_p->ad_register=reg_1;
+ if (result_graph->node_count>1)
+ float_register_node (result_graph,reg_1);
+ if (result_graph2->node_count>0)
+ float_register_node (result_graph2,reg_2);
+ else
+ free_fregister (reg_2);
+ } else {
+ ad_p->ad_register=reg_2;
+ if (result_graph->node_count>1)
+ float_register_node (result_graph,reg_2);
+ if (result_graph2->node_count>0)
+ float_register_node (result_graph2,reg_1);
+ else {
+ --*ad_1.ad_count_p;
+ free_fregister (reg_1);
+ }
+ }
+}
+#endif
+
static void linearize_float_graph (register INSTRUCTION_GRAPH graph,register ADDRESS *ad_p)
{
switch (graph->instruction_code){
@@ -6867,6 +7080,11 @@ static void linearize_float_graph (register INSTRUCTION_GRAPH graph,register ADD
case GFLOAD_X:
linearize_fload_x_operator (graph,ad_p);
return;
+#ifdef G_AI64
+ case GFLOAD_S_X:
+ linearize_fload_s_x_operator (graph,ad_p);
+ return;
+#endif
case GFADD:
linearize_dyadic_commutative_float_operator (IFADD,graph,ad_p);
return;
@@ -6941,6 +7159,12 @@ static void linearize_float_graph (register INSTRUCTION_GRAPH graph,register ADD
linearize_tof_operator (graph,ad_p);
return;
#endif
+#if defined (I486) && !defined (G_AI64)
+ case GFRESULT0:
+ case GFRESULT1:
+ linearize_two_float_results_operator (graph,ad_p);
+ return;
+#endif
default:
/* printf ("%d %d\n",(int)graph,graph->instruction_code); */
internal_error_in_function ("linearize_float_graph");
@@ -6965,7 +7189,10 @@ static void linearize_fstore_operator (INSTRUCTION_GRAPH graph)
move_float_ad_id (&ad_1,offset,stack_pointer);
}
-static void linearize_fstore_x_operator (register INSTRUCTION_GRAPH graph,register ADDRESS *ad_p);
+static void linearize_fstore_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p);
+#ifdef G_AI64
+static void linearize_fstore_s_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p);
+#endif
static void linearize_fstore_r_operator (register INSTRUCTION_GRAPH graph)
{
@@ -7320,6 +7547,75 @@ static void linearize_load_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p
}
}
+#ifdef G_AI64
+static void linearize_load_s_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p,int result_register)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2;
+ CleanInt offset;
+ int reg_1;
+
+ graph_1=graph->instruction_parameters[0].p;
+ offset=graph->instruction_parameters[1].imm;
+ graph_2=graph->instruction_parameters[2].p;
+
+ if (graph_2!=NULL){
+ ADDRESS ad_1;
+
+ if (graph->order_left){
+ linearize_graph (graph_1,ad_p);
+ linearize_graph (graph_2,&ad_1);
+ } else {
+ linearize_graph (graph_2,&ad_1);
+ linearize_graph (graph_1,ad_p);
+ }
+
+ in_data_register (&ad_1);
+ in_address_register (ad_p);
+
+ if (--*ad_p->ad_count_p==0)
+ free_aregister (ad_p->ad_register);
+
+ if (--*ad_1.ad_count_p==0)
+ free_dregister (ad_1.ad_register);
+
+ if (result_register!=0 && try_allocate_register_number (result_register>>1))
+ reg_1=result_register>>1;
+ else
+ if (graph->instruction_d_min_a_cost<=0)
+ reg_1=get_dregister();
+ else
+ reg_1=get_aregister();
+
+ i_loadsqb_x_r (offset,ad_p->ad_register,ad_1.ad_register,reg_1);
+ } else {
+ linearize_graph (graph_1,ad_p);
+ in_address_register (ad_p);
+
+ if (--*ad_p->ad_count_p==0)
+ free_aregister (ad_p->ad_register);
+
+ if (result_register!=0 && try_allocate_register_number (result_register>>1))
+ reg_1=result_register>>1;
+ else
+ if (graph->instruction_d_min_a_cost<=0)
+ reg_1=get_dregister();
+ else
+ reg_1=get_aregister();
+
+ i_loadsqb_id_r ((int)(offset>>4),ad_p->ad_register,reg_1);
+ }
+
+ ad_p->ad_mode=P_REGISTER;
+ ad_p->ad_register=reg_1;
+ ad_p->ad_count_p=&graph->node_count;
+
+ if (graph->node_count<=1)
+ graph->inode_arity=(graph->inode_arity & ~LOAD_X_TO_ADDRESS) | LOAD_X_TO_REGISTER;
+ else
+ register_node (graph,reg_1);
+}
+#endif
+
static void linearize_store_r_node (INSTRUCTION_GRAPH graph)
{
INSTRUCTION_GRAPH *register_graph_1_p,*register_graph_2_p;
@@ -7338,6 +7634,11 @@ static void linearize_store_r_node (INSTRUCTION_GRAPH graph)
linearize_load_x_operator (graph->instruction_parameters[1].p,&ad_1,(graph->instruction_parameters[0].i<<1)+1);
break;
#endif
+#ifdef G_AI64
+ case GLOAD_S_X:
+ linearize_load_s_x_operator (graph->instruction_parameters[1].p,&ad_1,(graph->instruction_parameters[0].i<<1)+1);
+ break;
+#endif
default:
linearize_graph (graph->instruction_parameters[1].p,&ad_1);
}
@@ -7515,9 +7816,9 @@ static void linearize_store_r_node (INSTRUCTION_GRAPH graph)
static void linearize_load_b_x_operator (register INSTRUCTION_GRAPH graph,register ADDRESS *ad_p)
{
- register INSTRUCTION_GRAPH graph_1,graph_2;
- register int offset;
-
+ INSTRUCTION_GRAPH graph_1,graph_2;
+ int offset;
+
graph_1=graph->instruction_parameters[0].p;
offset=graph->instruction_parameters[1].i;
graph_2=graph->instruction_parameters[2].p;
@@ -7733,6 +8034,19 @@ static void do_array_selects_before_update (INSTRUCTION_GRAPH select_graph,INSTR
}
}
break;
+#ifdef G_AI64
+ case GLOAD_S_X:
+ if (graph_2==select_graph->instruction_parameters[0].p){
+ if (select_graph->node_count>0 && !(select_graph->inode_arity & LOAD_X_TO_REGISTER)){
+ ADDRESS s_ad;
+
+ ++select_graph->node_count;
+ linearize_load_s_x_operator (select_graph,&s_ad,0);
+ --select_graph->node_count;
+ }
+ }
+ break;
+#endif
case GFLOAD_X:
#if 1
if (graph_2==select_graph->instruction_parameters[0].p){
@@ -7778,6 +8092,41 @@ static void do_array_selects_before_update (INSTRUCTION_GRAPH select_graph,INSTR
}
}
break;
+#ifdef G_AI64
+ case GFLOAD_S_X:
+ if (graph_2==select_graph->instruction_parameters[0].p){
+ if (select_graph->node_count>0 && !(select_graph->inode_arity & LOAD_X_TO_REGISTER)){
+ ADDRESS s_ad;
+
+ ++select_graph->node_count;
+ linearize_fload_s_x_operator (select_graph,&s_ad);
+ --select_graph->node_count;
+ } else if ((select_graph->inode_arity & LOAD_X_TO_ADDRESS) && select_graph!=graph_1){
+ ADDRESS *i_ad_p;
+ int freg;
+
+ i_ad_p=(ADDRESS *)select_graph->instruction_parameters[1].p;
+
+ select_graph->inode_arity ^= (LOAD_X_TO_ADDRESS | LOAD_X_TO_REGISTER);;
+
+ if (i_ad_p->ad_mode==P_INDEXED){
+ if (--*i_ad_p->ad_count_p==0)
+ free_aregister (i_ad_p->ad_areg);
+ if (--*i_ad_p->ad_count_p2==0)
+ free_dregister (i_ad_p->ad_dreg);
+ freg=get_fregister();
+ i_floads_x_fr (i_ad_p->ad_offset,i_ad_p->ad_areg,i_ad_p->ad_dreg,freg);
+ } else {
+ if (--*i_ad_p->ad_count_p==0)
+ free_aregister (i_ad_p->ad_register);
+ freg=get_fregister();
+ i_floads_id_fr (i_ad_p->ad_offset,i_ad_p->ad_register,freg);
+ }
+ i_ad_p->ad_register=freg;
+ }
+ }
+ break;
+#endif
case GREGISTER:
case GFREGISTER:
#ifndef G_A64
@@ -7798,7 +8147,7 @@ static void do_array_selects_before_update (INSTRUCTION_GRAPH select_graph,INSTR
}
}
-static void linearize_store_x_operator (int i_instruction_code,register INSTRUCTION_GRAPH graph,register ADDRESS *ad_p)
+static void linearize_store_x_operator (int i_instruction_code,INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
{
INSTRUCTION_GRAPH graph_1,graph_2,graph_3;
int offset;
@@ -7859,13 +8208,13 @@ static void linearize_store_x_operator (int i_instruction_code,register INSTRUCT
in_address_register (ad_p);
if (graph_3==NULL){
- if (i_instruction_code==IMOVEB && ad_1.ad_mode!=P_IMMEDIATE)
+ if (i_instruction_code!=IMOVE && ad_1.ad_mode!=P_IMMEDIATE)
in_data_register (&ad_1);
instruction_ad_id (i_instruction_code,&ad_1,offset>>2,ad_p->ad_register);
#if defined (sparc) || defined (G_POWER)
} else if (offset!=0){
- if (i_instruction_code==IMOVEB && ad_1.ad_mode!=P_IMMEDIATE)
+ if (i_instruction_code!=IMOVE && ad_1.ad_mode!=P_IMMEDIATE)
in_data_register (&ad_1);
instruction_ad_id (i_instruction_code,&ad_1,offset>>2,ad_3.ad_register);
@@ -7878,7 +8227,7 @@ static void linearize_store_x_operator (int i_instruction_code,register INSTRUCT
in_register (&ad_1);
#endif
- if (i_instruction_code==IMOVEB && ad_1.ad_mode!=P_IMMEDIATE
+ if (i_instruction_code!=IMOVE && ad_1.ad_mode!=P_IMMEDIATE
#ifdef M68000
&& ad_1.ad_mode!=P_INDEXED
#endif
@@ -8368,12 +8717,23 @@ static void linearize_graph (INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
case GLOAD_B_X:
linearize_load_b_x_operator (graph,ad_p);
return;
+#ifdef G_AI64
+ case GLOAD_S_X:
+ linearize_load_s_x_operator (graph,ad_p,0);
+ return;
+#endif
case GSTORE_X:
linearize_store_x_operator (IMOVE,graph,ad_p);
return;
case GSTORE_B_X:
linearize_store_x_operator (IMOVEB,graph,ad_p);
return;
+#ifdef G_AI64
+ case GSTORE_S_X:
+ graph->instruction_parameters[2].i = graph->instruction_parameters[2].imm>>2;
+ linearize_store_x_operator (IMOVEQB,graph,ad_p);
+ return;
+#endif
case GSTORE_R:
linearize_store_r_node (graph);
break;
@@ -8383,6 +8743,11 @@ static void linearize_graph (INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
case GFSTORE_X:
linearize_fstore_x_operator (graph,ad_p);
return;
+#ifdef G_AI64
+ case GFSTORE_S_X:
+ linearize_fstore_s_x_operator (graph,ad_p);
+ return;
+#endif
case GFSTORE_R:
linearize_fstore_r_operator (graph);
return;
@@ -8562,9 +8927,7 @@ static void linearize_graph (INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
}
}
-#pragma segment Code30
-
-static void linearize_fstore_x_operator (register INSTRUCTION_GRAPH graph,register ADDRESS *ad_p)
+static void linearize_fstore_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
{
INSTRUCTION_GRAPH graph_1,graph_2,graph_3;
int offset;
@@ -8680,6 +9043,111 @@ static void linearize_fstore_x_operator (register INSTRUCTION_GRAPH graph,regist
}
}
+#ifdef G_AI64
+static void linearize_fstore_s_x_operator (INSTRUCTION_GRAPH graph,ADDRESS *ad_p)
+{
+ INSTRUCTION_GRAPH graph_1,graph_2,graph_3;
+ int offset;
+ ADDRESS ad_1,ad_3;
+
+ graph_1=graph->instruction_parameters[0].p;
+ graph_2=graph->instruction_parameters[1].p;
+ offset=graph->instruction_parameters[2].i;
+ graph_3=graph->instruction_parameters[3].p;
+
+ if (graph_3==NULL){
+ if (graph->order_left){
+ linearize_float_graph (graph_1,&ad_1);
+ linearize_graph (graph_2,ad_p);
+ } else {
+ linearize_graph (graph_2,ad_p);
+ linearize_float_graph (graph_1,&ad_1);
+ }
+ } else {
+ switch (graph->order_left){
+ case 0:
+ linearize_float_graph (graph_1,&ad_1);
+ linearize_graph (graph_2,ad_p);
+ linearize_graph (graph_3,&ad_3);
+ break;
+ case 1:
+ linearize_float_graph (graph_1,&ad_1);
+ linearize_graph (graph_3,&ad_3);
+ linearize_graph (graph_2,ad_p);
+ break;
+ case 2:
+ linearize_graph (graph_2,ad_p);
+ linearize_float_graph (graph_1,&ad_1);
+ linearize_graph (graph_3,&ad_3);
+ break;
+ case 3:
+ linearize_graph (graph_2,ad_p);
+ linearize_graph (graph_3,&ad_3);
+ linearize_float_graph (graph_1,&ad_1);
+ break;
+ case 4:
+ linearize_graph (graph_3,&ad_3);
+ linearize_graph (graph_2,ad_p);
+ linearize_float_graph (graph_1,&ad_1);
+ break;
+ case 5:
+ linearize_graph (graph_3,&ad_3);
+ linearize_float_graph (graph_1,&ad_1);
+ linearize_graph (graph_2,ad_p);
+ break;
+ default:
+ internal_error_in_function ("linearize_fstore_s_x_operator");
+ }
+ }
+
+ do_array_selects_before_update (graph->instruction_parameters[4].p,graph_1,graph_2);
+
+ in_address_register (ad_p);
+
+ if (graph_3==NULL){
+ int reg_1;
+
+ if (ad_1.ad_mode!=P_F_REGISTER)
+ in_float_register (&ad_1);
+
+ if (--*ad_1.ad_count_p==0)
+ reg_1=ad_1.ad_register;
+ else
+ reg_1=get_fregister();
+
+ i_fcvt2s_fr_fr (ad_1.ad_register,reg_1);
+ i_fmoves_fr_id (reg_1,offset>>2,ad_p->ad_register);
+
+ free_fregister (reg_1);
+ } else {
+ int reg_1;
+
+ in_data_register (&ad_3);
+
+ if (--*ad_3.ad_count_p==0)
+ free_dregister (ad_3.ad_register);
+
+ if (ad_1.ad_mode!=P_F_REGISTER)
+ in_float_register (&ad_1);
+
+ if (--*ad_1.ad_count_p==0)
+ reg_1=ad_1.ad_register;
+ else
+ reg_1=get_fregister();
+
+ i_fcvt2s_fr_fr (ad_1.ad_register,reg_1);
+ i_fmoves_fr_x (reg_1,offset,ad_p->ad_register,ad_3.ad_register);
+
+ free_fregister (reg_1);
+ }
+
+ if (graph->node_count>1){
+ register_node (graph,ad_p->ad_register);
+ ad_p->ad_count_p=&graph->node_count;
+ }
+}
+#endif
+
void calculate_and_linearize_branch_false (LABEL *label,INSTRUCTION_GRAPH graph)
{
int condition,condition_on_stack;
diff --git a/cgopt.c b/cgopt.c
index 0f7e22c..a248660 100644
--- a/cgopt.c
+++ b/cgopt.c
@@ -51,8 +51,6 @@
# define OPTIMIZE_LOOPS
#endif
-#pragma segment Code4
-
/* from cgcode.c : */
extern struct basic_block *first_block;
@@ -1595,7 +1593,10 @@ IF_G_POWER ( case IUMULH: )
#ifndef I486_USE_SCRATCH_REGISTER
case IMOVE:
#endif
- case IMOVEB: case IMOVEW:
+ case IMOVEB: case IMOVEDB:
+#ifdef G_AI64
+ case IMOVEQB:
+#endif
case IFCOS: case IFSIN: case IFTAN:
#ifdef M68000
case IFACOS: case IFASIN: case IFATAN: case IFEXP: case IFLN: case IFLOG10:
@@ -1608,7 +1609,10 @@ IF_G_POWER ( case IUMULH: )
IF_G_SPARC (case IFMOVEHI: case IFMOVELO:)
IF_G_RISC (case IADDI: case ILSLI:)
#ifdef G_AI64
- case IMOVESW:
+ case ILOADSQB: case IFLOADS: case IFCVT2S: case IFMOVES:
+#endif
+#if defined (I486) && !defined (G_A64)
+ case IFSINCOS:
#endif
define_parameter (&instruction->instruction_parameters[1]);
use_parameter (&instruction->instruction_parameters[0]);
@@ -3897,7 +3901,10 @@ IF_G_POWER (case ICMPLW:)
#ifndef I486_USE_SCRATCH_REGISTER
case IMOVE:
#endif
- case IMOVEB: case IMOVEW:
+ case IMOVEB: case IMOVEDB:
+#ifdef G_AI64
+ case IMOVEQB:
+#endif
case IFCOS: case IFSIN: case IFTAN:
#ifdef M68000
case IFACOS: case IFASIN: case IFATAN: case IFEXP: case IFLN: case IFLOG10:
@@ -3910,7 +3917,7 @@ IF_G_POWER (case ICMPLW:)
IF_G_SPARC (case IFMOVEHI: case IFMOVELO:)
IF_G_RISC (case IADDI: case ILSLI:)
#ifdef G_AI64
- case IMOVESW:
+ case ILOADSQB: case IFLOADS: case IFCVT2S: case IFMOVES:
#endif
#if 1
if (instruction->instruction_parameters[1].parameter_type==P_REGISTER ||
@@ -4033,6 +4040,14 @@ IF_G_RISC (case IADDI: case ILSLI:)
case IBEQ: case IBGE: case IBGT: case IBLE: case IBLT: case IBNE:
case IBO: case IBGEU: case IBGTU: case IBLEU: case IBLTU: case IBNO:
break;
+#if defined (I486) && !defined (G_A64)
+ case IFSINCOS:
+ use_2_same_type_registers
+ (&instruction->instruction_parameters[0].parameter_data.reg,USE_DEF,
+ &instruction->instruction_parameters[1].parameter_data.reg,DEF,
+ F_REGISTER);
+ break;
+#endif
default:
internal_error_in_function ("allocate_registers");
}
diff --git a/cgpas.c b/cgpas.c
index d2e536d..cc53b73 100644
--- a/cgpas.c
+++ b/cgpas.c
@@ -463,7 +463,7 @@ static void as_branch_label (struct label *label,int relocation_kind)
new_relocation->kind=relocation_kind;
}
-enum { SIZE_LONG, SIZE_WORD, SIZE_BYTE };
+enum { SIZE_QBYTE, SIZE_DBYTE, SIZE_BYTE };
#define REGISTER_O0 (-13)
#define REGISTER_O1 (-23)
@@ -753,27 +753,27 @@ static int as_register_parameter (struct parameter parameter,int size_flag)
case P_REGISTER:
return parameter.parameter_data.reg.r;
case P_INDIRECT:
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_lwz (REGISTER_O0,parameter.parameter_offset,parameter.parameter_data.reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_lha (REGISTER_O0,parameter.parameter_offset,parameter.parameter_data.reg.r);
else
as_lbz (REGISTER_O0,parameter.parameter_offset,parameter.parameter_data.reg.r);
return REGISTER_O0;
case P_INDIRECT_WITH_UPDATE:
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_lwzu (REGISTER_O0,parameter.parameter_offset,parameter.parameter_data.reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_lhau (REGISTER_O0,parameter.parameter_offset,parameter.parameter_data.reg.r);
else
as_lbzu (REGISTER_O0,parameter.parameter_offset,parameter.parameter_data.reg.r);
return REGISTER_O0;
case P_INDEXED:
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_lwzx (REGISTER_O0,parameter.parameter_data.ir->a_reg.r,parameter.parameter_data.ir->d_reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_lhax (REGISTER_O0,parameter.parameter_data.ir->a_reg.r,parameter.parameter_data.ir->d_reg.r);
else
as_lbzx (REGISTER_O0,parameter.parameter_data.ir->a_reg.r,parameter.parameter_data.ir->d_reg.r);
@@ -818,12 +818,12 @@ static void as_move_instruction (struct instruction *instruction,int size_flag)
instruction->instruction_parameters[0].parameter_data.reg.r);
return;
case P_INDIRECT:
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_lwz (
instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[0].parameter_offset,
instruction->instruction_parameters[0].parameter_data.reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_lha (
instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[0].parameter_offset,
@@ -835,12 +835,12 @@ static void as_move_instruction (struct instruction *instruction,int size_flag)
instruction->instruction_parameters[0].parameter_data.reg.r);
return;
case P_INDIRECT_WITH_UPDATE:
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_lwzu (
instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[0].parameter_offset,
instruction->instruction_parameters[0].parameter_data.reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_lhau (
instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[0].parameter_offset,
@@ -852,12 +852,12 @@ static void as_move_instruction (struct instruction *instruction,int size_flag)
instruction->instruction_parameters[0].parameter_data.reg.r);
return;
case P_INDEXED:
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_lwzx (
instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[0].parameter_data.ir->a_reg.r,
instruction->instruction_parameters[0].parameter_data.ir->d_reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_lhax (
instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[0].parameter_data.ir->a_reg.r,
@@ -878,11 +878,11 @@ static void as_move_instruction (struct instruction *instruction,int size_flag)
reg=as_register_parameter (instruction->instruction_parameters[0],size_flag);
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_stw (reg,
instruction->instruction_parameters[1].parameter_offset,
instruction->instruction_parameters[1].parameter_data.reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_sth (reg,
instruction->instruction_parameters[1].parameter_offset,
instruction->instruction_parameters[1].parameter_data.reg.r);
@@ -898,11 +898,11 @@ static void as_move_instruction (struct instruction *instruction,int size_flag)
reg=as_register_parameter (instruction->instruction_parameters[0],size_flag);
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_stwu (reg,
instruction->instruction_parameters[1].parameter_offset,
instruction->instruction_parameters[1].parameter_data.reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_sthu (reg,
instruction->instruction_parameters[1].parameter_offset,
instruction->instruction_parameters[1].parameter_data.reg.r);
@@ -918,11 +918,11 @@ static void as_move_instruction (struct instruction *instruction,int size_flag)
reg=as_register_parameter (instruction->instruction_parameters[0],size_flag);
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_stwx (reg,
instruction->instruction_parameters[1].parameter_data.ir->a_reg.r,
instruction->instruction_parameters[1].parameter_data.ir->d_reg.r);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_sthx (reg,
instruction->instruction_parameters[1].parameter_data.ir->a_reg.r,
instruction->instruction_parameters[1].parameter_data.ir->d_reg.r);
@@ -947,9 +947,9 @@ static void as_move_instruction (struct instruction *instruction,int size_flag)
offset=(WORD)offset;
}
- if (size_flag==SIZE_LONG)
+ if (size_flag==SIZE_QBYTE)
as_stw (reg1,offset,reg2);
- else if (size_flag==SIZE_WORD)
+ else if (size_flag==SIZE_DBYTE)
as_sth (reg1,offset,reg2);
else
as_stb (reg1,offset,reg2);
@@ -1020,7 +1020,7 @@ static void as_add_instruction (struct instruction *instruction)
{
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_add (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1041,7 +1041,7 @@ static void as_addo_instruction (struct instruction *instruction)
{
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_addo_ (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1075,7 +1075,7 @@ static void as_sub_instruction (struct instruction *instruction)
{
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_sub (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1087,7 +1087,7 @@ static void as_subo_instruction (struct instruction *instruction)
{
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_subo_ (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1254,7 +1254,7 @@ static void as_slw_instruction (struct instruction *instruction)
} else {
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_slw (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1270,7 +1270,7 @@ static void as_srw_instruction (struct instruction *instruction)
} else {
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_srw (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1286,7 +1286,7 @@ static void as_sraw_instruction (struct instruction *instruction)
} else {
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_sraw (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1321,7 +1321,7 @@ static void as_mul_instruction (struct instruction *instruction)
break;
}
default:
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
}
as_mullw (r,r,reg);
@@ -1333,7 +1333,7 @@ static void as_umulh_instruction (struct instruction *instruction)
r=instruction->instruction_parameters[1].parameter_data.reg.r;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_mulhwu (r,r,reg);
}
@@ -1342,7 +1342,7 @@ static void as_mulo_instruction (struct instruction *instruction)
{
int r,reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
r=instruction->instruction_parameters[1].parameter_data.reg.r;
@@ -1457,7 +1457,7 @@ static void as_div_instruction (struct instruction *instruction)
}
}
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_divw (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1467,7 +1467,7 @@ static void as_divu_instruction (struct instruction *instruction)
{
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_divwu (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1557,7 +1557,7 @@ static void as_rem_instruction (struct instruction *instruction)
}
}
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_divw (REGISTER_O1,instruction->instruction_parameters[1].parameter_data.reg.r,reg);
as_mullw (REGISTER_O1,REGISTER_O1,reg);
@@ -1603,7 +1603,7 @@ static void as_and_instruction (struct instruction *instruction)
reg=REGISTER_O0;
}
} else
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_and (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1632,7 +1632,7 @@ static void as_or_instruction (struct instruction *instruction)
} else {
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_or (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1662,7 +1662,7 @@ static void as_xor_instruction (struct instruction *instruction)
} else {
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_xor (instruction->instruction_parameters[1].parameter_data.reg.r,
instruction->instruction_parameters[1].parameter_data.reg.r,reg);
@@ -1673,7 +1673,7 @@ static void as_tst_instruction (struct instruction *instruction)
{
int reg;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_cmpi (reg,0);
}
@@ -2728,7 +2728,7 @@ static void as_fmovel_instruction (struct instruction *instruction)
int reg;
struct label *new_label;
- reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_LONG);
+ reg=as_register_parameter (instruction->instruction_parameters[0],SIZE_QBYTE);
as_new_data_module();
@@ -2771,7 +2771,7 @@ static void write_instructions (struct instruction *instructions)
for_l (instruction,instructions,instruction_next){
switch (instruction->instruction_icode){
case IMOVE:
- as_move_instruction (instruction,SIZE_LONG);
+ as_move_instruction (instruction,SIZE_QBYTE);
break;
case ILEA:
as_lea_instruction (instruction);
@@ -2910,8 +2910,8 @@ static void write_instructions (struct instruction *instructions)
case IBTST:
as_btst_instruction (instruction);
break;
- case IMOVEW:
- as_move_instruction (instruction,SIZE_WORD);
+ case IMOVEDB:
+ as_move_instruction (instruction,SIZE_DBYTE);
break;
case IMOVEB:
as_move_instruction (instruction,SIZE_BYTE);
diff --git a/cgpwas.c b/cgpwas.c
index d2bd19b..aae0098 100644
--- a/cgpwas.c
+++ b/cgpwas.c
@@ -3272,7 +3272,7 @@ static void w_as_instructions (register struct instruction *instruction)
case IBTST:
w_as_btst_instruction (instruction);
break;
- case IMOVEW:
+ case IMOVEDB:
w_as_move_instruction (instruction,SIZE_WORD);
break;
case IMOVEB:
diff --git a/cgsas.c b/cgsas.c
index 9f60c7e..a763f7d 100644
--- a/cgsas.c
+++ b/cgsas.c
@@ -1868,7 +1868,7 @@ static void as_instructions (register struct instruction *instruction)
case IBTST:
as_btst_instruction (instruction);
break;
- case IMOVEW:
+ case IMOVEDB:
as_move_instruction (instruction,SIZE_WORD);
break;
case IMOVEB:
diff --git a/cgswas.c b/cgswas.c
index c738280..6b4aa94 100644
--- a/cgswas.c
+++ b/cgswas.c
@@ -2160,7 +2160,7 @@ static void w_as_instructions (register struct instruction *instruction)
case IBTST:
w_as_btst_instruction (instruction);
break;
- case IMOVEW:
+ case IMOVEDB:
w_as_move_instruction (instruction,SIZE_WORD);
break;
case IMOVEB:
diff --git a/cgwas.c b/cgwas.c
index 4958d3c..fa6e809 100644
--- a/cgwas.c
+++ b/cgwas.c
@@ -1179,7 +1179,7 @@ static void w_as_instructions (register struct instruction *instruction)
case ITST:
w_as_tst_instruction (instruction);
break;
- case IMOVEW:
+ case IMOVEDB:
w_as_move_instruction (instruction,SIZE_WORD);
break;
case IMOVEB:
generated by cgit v1.2.3 (git 2.39.1) at 2025-03-16 04:45:58 +0000